6.3.1 OTP memory map
The OTP memory locations are as defined in Table 10. The OTP memory locations are each 32-bits wide, OTP
addresses are word addresses so each increment of address specifies a different 32-bit word.
Table 10: OTP memory map
64 bit EUID
(These 64 bits get automatically copied over to Register File 0x01:EUI on each reset.)
40 bit LDOTUNE_CAL
(These 40 bits can be automatically copied over to Sub Register File 0x28:30 LDOTUNE
on wakeup)
{“0001,0000,0000“, "CHIP ID (20 bits)"}
{“0001”“, "LOT ID (28 bits)"}
Customer / Deca-
wave Test
CH1 TX Power Level PRF 16
CH1 TX Power Level PRF 64
CH2 TX Power Level PRF 16
CH2 TX Power Level PRF 64
CH3 TX Power Level PRF 16
CH3 TX Power Level PRF 64
CH4 TX Power Level PRF 16
CH4 TX Power Level PRF 64
CH5 TX Power Level PRF 16
CH5 TX Power Level PRF 64
CH7 TX Power Level PRF 16
CH7 TX Power Level PRF 64
TX/RX Antenna Delay – PRF 64
TX/RX Antenna Delay – PRF 16