decaWave DW1000 - Page 156

DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 156 of 242
Field
Description of fields within Sub-Register 0x28:2C – RF_STATUS
CPLLLOCK
reg:28:2C
bit:0
Clock PLL Lock status. This is a READ ONLY status flag. CPLLLOCK indicates that the digital clock
PLL is locked. Note: The PLLLDT bit in Register file 0x24:00 –EC_CTRL should be set to ensure
reliable operation of this CPLLLOCK bit.
CPLLLOW
reg:28:2C
bit:1
Clock PLL Low flag status bit. This indicates PLL is running a little lower than its target
frequency, which may be an early indication of lock issues.
CPLLHIGH
reg:28:2C
bit:2
Clock PLL High flag status bit. This indicates PLL is running a little higher than its target
frequency, which may be an early indication of lock issues.
RFPLLLOCK
reg:28:2C
bit:3
RF PLL Lock status. This is a READ ONLY status flag. CPLLLOCK indicates that the RF PLL is
locked. Note that this lock detect flag may not be reliable and is only used for debug
purposes.
-
reg:28:2C
bits:31–4
Reserved. The remainder of this register is reserved.
7.2.41.7 Sub-Register 0x28:30 – LDOTUNE
ID
Length
(octets)
Type
Mnemonic
Description
28:30
5
RW
LDOTUNE
Internal LDO voltage tuning parameter
REG:28:30 – LDOTUNE – LDO voltage tuning
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LDOTUNE
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
REG:28:30 – LDOTUNE – LDO voltage tuning
39
38
37
36
35
34
33
32
LDOTUNE
1
0
0
0
1
0
0
0
Register file: 0x28 – Analog RF configuration block, sub-register 0x30 is the LDO voltage tuning register.
Please take care not to write to this register unless you are loading the calibrated value from OTP.
Field
Description of fields within Sub-Register 0x28:30 – LDOTUNE
LDOTUNE
reg:28:30
bits:39:0
This register is used to control the output voltage levels of the on chip LDOs. If configured to
do so, this register can be automatically loaded from the OTP if a non-default value is
required, otherwise the default should be used. Ensure that the LDOTUNE_CAL OTP value is
programmed before attempting to copy it over to this address. To automatically load the
OTP value in to this register see Sub Register 0x2C:0 – AON_WCFG bit 12.