decaWave DW1000 - Table 53: Register File

DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 198 of 242
7.2.50.3 Sub-Register 0x36:08 – PMSC_RES1
ID
Length
(octets)
Type
Mnemonic
Description
36:08
4
RW
PMSC_RES1
PMSC reserved area 1
Register file: 0x36 – Power Management and System Control, sub-register 0x08 is a reserved register. Please
take care not to write to this register as doing so may cause the DW1000 to malfunction.
7.2.50.4 Sub-Register 0x36:0C – PMSC_SNOZT
ID
Length
(octets)
Type
Mnemonic
Description
36:0C
1
RW
PMSC_SNOZT
PMSC Snooze Time Register
Register file: 0x36 – Power Management and System Control, sub-register 0x0C is an 8-bit register for
specifying the snooze time period. The PMSC_SNOZT register contains the following sub-fields:
REG:36:0C – PMSC_SNOZT – PMSC Snooze Time Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SNOZ_TIM
0
1
0
0
0
0
0
0
The fields of the PMSC_CTRL1 register identified above are individually described below:
Field
Description of fields within Sub-Register 0x36:0C – PMSC_SNOZT
SNOZ_TIM
reg:36:0C
bits:7–0
Snooze Time Period. These bits are the upper 8-bits of a 17-bit timer that defines the snooze
period in units of the 19.2 MHz XTI internal clock. The default value 0x40 (or decimal 64), gives
a period of 64×512/19.2e6 seconds, or 1.7 ms. Snoozing is enabled via the SNOZE bit in Sub-
Register 0x36:04 – PMSC_CTRL1, and is used during low power listening. See section 4.4 –
Low-Power Listening for more details.
Note that the counter automatically adds 1 to the programmed value so SNOZ_TIM should
be programmed to be 1 less than the desired value.
7.2.50.5 Sub-Register 0x36:10 – PMSC_RES2
ID
Length
(octets)
Type
Mnemonic
Description
36:10
22
RW
PMSC_RES2
PMSC reserved area 2
Register file: 0x36 – Power Management and System Control, sub-register 0x10 is a reserved register. Please
take care not to write to this register as doing so may cause the DW1000 to malfunction.