Term used to refer to the receiver section of a transceiver or the operation
of receiving signals
Successive
Approximation
Register ADC
A type of Analog to Digital converter that used a digital binary search to
converge on the correct digital representation of the analog input level.
single error
correct, double
error detect (a
parity check
sequence in the
PHR)
A coding scheme that allows the: -
detection and correction of a single bit error in a group of bits or
the detection but not the correction of a double bit error in a group of
bits
The IEEE802.15.4-2011 UWB standard defines the use of such a scheme as
a parity check in the PHR portion of the frame.
Defined in the context of the IEEE802.15.4-2011 [1] standard. Indicates
the completion of the preamble section of the frame and the
commencement of the payload section.
synchronisation
header (consists of
preamble and
SFD)
Defined in the context of the IEEE802.15.4-2011 [1] standard. The first
portion of an IEEE802.15.4-2011 UWB frame containing the preamble and
SFD
serial peripheral
interface
An industry accepted method for interfacing between IC’s using a
synchronous serial scheme first introduced by Motorola
time difference of
arrival
Method of deriving information on the location of a transmitter. The time
of arrival of a transmission at two physically different locations whose
clocks are synchronized is noted and the difference in the arrival times
provides information on the location of the transmitter. A number of such
TDOA measurements at different locations can be used to uniquely
determine the position of the transmitter. Refer to Decawave’s website
for further information.
The time taken for a radio signal to travel between the transmitting
antenna and the receiving antenna
Term used to refer to the transmitter section of a transceiver or the
operation of transmitting signals
A radio scheme employing channel bandwidths of, or in excess of, 500MHz
A network of wireless nodes intended to enable the monitoring and
control of the physical environment
internal 19.2 MHz
clock (is the raw
38.4 MHz XTAL
oscillator input
÷ 2)
The 38.4 MHz XTAL oscillator clock divided by 2.
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