Description of fields within Sub-Register 0x36:00 – PMSC_CTRL0
SOFTRESET
reg:36:00
bits:31–28
These four bits reset the IC TX, RX, Host Interface and the PMSC itself, essentially allowing a
reset of the IC under software control. These bits should be cleared to zero to force a reset
and then returned to one for normal operation. The correct procedure to achieve this reset is
to:
(a) Set SYSCLKS to 01
(b) Clear SOFTRESET to all zero’s
(c) Set SOFTRESET to all ones
The AON block is not reset by this activity and so may take action following the reset
depending on the configuration within Sub-Register 0x2C:00 – AON_WCFG.
To apply a receiver-only soft reset, clear and set bit 28 only.
7.2.50.2 Sub-Register 0x36:04 – PMSC_CTRL1
Register file: 0x36 – Power Management and System Control, sub-register 0x04 is a 32-bit control register.
The PMSC_CTRL1 register contains the following sub-fields:
REG:36:04 – PMSC_CTRL1 – PMSC Control Register 1
The fields of the PMSC_CTRL1 register identified above are individually described below:
Description of fields within Sub-Register 0x36:04 – PMSC_CTRL1
Bits marked ‘-’ are reserved and should be preserved at their reset value.
Automatic transition from receive mode into the INIT state. If the ARX2INIT bit is set then the
DW1000 will automatically transition into the INIT state after a receive attempt so long as
there are no unmasked interrupts pending. This control is used to enableLow duty-cycle SNIFF
mode. Please refer to section 4.5.2 – Low duty-cycle SNIFF mode for more details of this
functionality.
PKTSEQ
reg:36:04
bits:10-3
Writing 0 to PKTSEQ disables PMSC control of analog RF subsystems. To enable PMSC control
of these blocks a value of 0xE7 should be written.
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