Description of fields within Sub-Register 0x36:04 – PMSC_CTRL1
After TX automatically Sleep. If this bit is set then the DW1000 will automatically transition
into SLEEP or DEEPSLEEP mode after transmission of a frame has completed so long as there
are no unmasked interrupts pending. This bit is cleared when the DW1000 wakes from sleep,
unless the as the PRES_SLEEP bit is set in Sub-Register 0x2C:00 – AON_WCFG. Before using this
ATXSLP feature the AON configurations in Register file: 0x2C – Always-on system control
interface should be set to allow for the appropriate DW1000 wakeup functionality. One of the
uses for this would be in a device that periodically transmits a message (e.g. TDOA RTLS Tag) to
return the DW1000 to its lowest power state immediately after the transmission, saving
power.
NOTE: SLEEP_EN bit in Sub-Register 0x2C:06 – AON_CFG0 has to be set to enable this
functionality.
After RX automatically Sleep. If this bit is set then the DW1000 will automatically transition
into SLEEP mode after a receive attempt so long as there are no unmasked interrupts pending.
Before using ARXSLP the AON configurations in Register file: 0x2C – Always-on system control
interface should be set to allow for the appropriate DW1000 wakeup functionality. This bit is
cleared when the DW1000 wakes from sleep, unless the as the PRES_SLEEP bit is set in Sub-
Register 0x2C:00 – AON_WCFG.One of the uses for this is to implement a scheme called Low-
Power Listening. See section 4.4 – Low-Power Listening for more details.
NOTE: SLEEP_EN bit in Sub-Register 0x2C:06 – AON_CFG0 has to be set to enable this
functionality.
Snooze Enable. A SNOOZE is like a SLEEP except the snooze uses the 19.2 MHz XTI clock and
the snooze time period is specified by the SNOZ_TIM field of Sub-Register 0x36:0C –
PMSC_SNOZT. Snoozing is more precisely timed than sleeping but has a higher power drain
than sleeping. This is used to implement the Low-Power Listening scheme, see section 4.4 –
Low-Power Listening for more details.
Snooze Repeat. The SNOZR bit is set to allow the snooze timer to repeat indefinitely. SNOOZE-
> RX-> SNOOZE-> RX->etc.
This enables a special 1 GHz clock used for some external SYNC modes. If this is not required
then to save power the PLLSYN configuration should be left set to 0. See Register file: 0x24 –
External Synchronisation Control for more details.
LDE run enable. This bit enables the running of the LDE algorithm. LDERUNE is 1 by default
which means that the LDE algorithm will be run as soon as the SFD is detected in the receiver.
When LDERUNE is set to zero the LDE algorithm will not be run and the RX_STAMP in Register
file: 0x15 – Receive Time Stamp will not be updated. For this the LDE code needs to be loaded
from ROM into its runtime RAM, which is achieved using the LDELOAD control in Sub-Register
0x2D:06 – OTP_CTRL, an can also be done automatically when waking from SLEEP or
DEEPSLEEP via the ONW_LLDE control in Sub-Register 0x2C:00 – AON_WCFG. If the LDE code is
not loaded then the LDERUNE control must be disabled before turning on the receiver.
KHZCLKDIV
reg:36:04
bits:31–26
Kilohertz clock divisor. This field specifies a clock divider designed to give a kilohertz range
clock that is used in the DW1000 for the LED blink functionality and also for the GPIO de-
bounce functionality. The input to the kHz divider is the 19.2 MHz XTI clock (which is the raw
38.4 MHz XTAL ÷ 2). The KHZCLKDIV field specifies the top 6 bits of a 10-bit counter allowing
divisors up to 2016 or clock frequencies from 9.5 kHz up to 600 kHz. The resultant clock is used
directly in the GPIO de-bounce circuit (see Sub-Register 0x26:24 – GPIO_IDBE). A further
divider is applied for the LED blink functionality, see Sub-Register 0x36:28 – PMSC_LEDC.
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