EasyManua.ls Logo

decaWave DW1000 - Page 175

decaWave DW1000
242 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 175 of 242
OFFSET in Register 0x2D
Mnemonic
Description
0x0E
OTP_SRDAT
OTP SR Read Data
0x12
OTP_SF
OTP Special Function
7.2.46.1 Sub-Register 0x2D:00 OTP_WDAT
ID
Length
(octets)
Type
Mnemonic
Description
2D:00
4
RW
OTP_WDAT
OTP Write Data
Register file: 0x2D OTP Memory Interface, sub-register 0x00 is a 32-bit register. The data value to be
programmed into an OTP location should be written here before invoking the programming function.
Writing to OTP memory is an involved procedure. For details of this please refer to section 6.3.2
Programming a value into OTP memory.
7.2.46.2 Sub-Register 0x2D:04 OTP_ADDR
ID
Length
(octets)
Type
Mnemonic
Description
2D:04
2
RW
OTP_ADDR
OTP Address
Register file: 0x2D OTP Memory Interface, sub-register 0x04 is a 16-bit register used to select the address
within the OTP memory block that is being accessed (for read or write) this OTP memory interface. The
OTP_ADDR register contains the following fields:
REG:2D:04 OTP_ADDR OTP Address
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
OTPADDR
-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
The fields of the OTP_ADDR register are described below:
Field
Description of fields within Sub-Register 0x2D:04 OTP_ADDR
OTPADDR
reg:2D:04
bits:10 0
This 11-bit field specifies the address within OTP memory that will be accessed read or written.
For details of the OTP memory map and the procedures to read and write OTP memory, please
refer to section 6.3 Using the on-chip OTP memory.
-
reg:2D:04
bits:15 11
Reserved. The remainder of this register is reserved.
7.2.46.3 Sub-Register 0x2D:06 OTP_CTRL
ID
Length
(octets)
Type
Mnemonic
Description
2D:06
2
RW
OTP_CTRL
OTP Control

Table of Contents