Description of fields within Sub-Register 0x2C:00 – AON_WCFG
On Wake-up load the Length64 receiver operating parameter set. When the ONW_L64P bit
is set to 1 the Length64receiver operating parameter set is selected when the DW1000
wakes from SLEEP or DEEPSLEEP or is reset. When the ONW_L64P bit is 0 the receiver
operating parameter set reverts to its power-on-reset value (the default operating
parameter set) when the DW1000 wakes from SLEEP or DEEPSLEEP or is reset. For details
of receiver operating parameter set see section 7.2.46.8 – Receiver operating parameter
sets.
NB: This bit needs to be clear for reset to select the default operating parameter set.
PRES_SLEEP
reg:2C:00
bit:8
Preserve Sleep. This bit determines what the DW1000 does with respect to the ARXSLP and
ATXSLP sleep controls in Sub-Register 0x36:04 – PMSC_CTRL1 after a wake-up event. When
the PRES_SLEEP bit is set to 1 these sleep controls are not cleared upon wakeup, so that the
DW1000 can return to sleep after a failed reception (say). This needs to be set for correct
operation of call Low-Power Listening. See section 4.4 – Low-Power Listening for more
details of the required configurations.
ONW_LLDE
reg:2C:00
bit:11
On Wake-up load the LDE microcode. The LDE algorithm is implemented in a microcode
that is stored in a special ROM area on the DW1000 but run from a RAM area. Before the
LDE is run the DW1000 has to copy it from ROM to RAM. The LDE algorithm is responsible
for generating an accurate RX timestamp and calculating some signal quality statistics
related to the received packet. See Register file: 0x2E – Leading Edge Detection Interface
for more details about the LDE functionality. If the DW1000 is waking up to receive a
frame and it is important to timestamp this received frame then the ONW_LLDE bit should
be set to 1 to cause the LDE to be loaded into RAM. If time-stamping is not required then
ONW_LLDE bit may be left set to 0 to save this loading and save some energy in the
process.
ONW_LLD0
reg:2C:00
bit:12
On Wake-up load the LDOTUNE value from OTP. When the DW1000 wakes up from SLEEP
or DEEPSLEEP states the value stored in OTP address 0x4 will be automatically written in to
Sub-Register 0x28:0x30 -
7.2.45.2 Sub-Register 0x2C:02 – AON_CTRL
Register file: 0x2C – Always-on system control, sub-register 0x02 is an 8-bit control register. The bits in this
register in general cause direct activity within the AON block with respect to the stored AON memory. The
bits then act like commands that are processed by the DW1000 and the bits are automatically cleared as the
activity is taken.
The AON_CTRL register contains the following control bits:
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