decaWave DW1000 - Page 168

DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 168 of 242
REG:2C:02 – AON_CTRL – AON Control Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DCA_ENAB
-
-
-
DCA_READ
UPL_CFG
SAVE
RESTORE
0
0
0
0
0
0
0
0
Definition of the bit fields within Sub-Register 0x2C:02 – AON_CTRL:
Field
Description of fields within Sub-Register 0x2C:02 – AON_CTRL
RESTORE
reg:2C:02
bit:0
When this bit is set the DW1000 will copy the user configurations from the AON memory to
the host interface register set. The RESTORE bit will auto clear when this command is
executed.
SAVE
reg:2C:02
bit:1
When this bit is set the DW1000 will copy the user configurations from the host interface
register set into the AON memory. It will then proceed to upload the AON block
configurations. The SAVE bit will auto clear when this command is executed.
UPL_CFG
reg:2C:02
bit:2
Upload the AON block configurations to the AON. This control will copy the AON
configurations of the two registers: Sub-Register 0x2C:06 – AON_CFG0 and Sub-Register
0x2C:0A – AON_CFG1 into the AON configuration registers. This may be done for instance
to enter SLEEP mode after correctly configuring it in those two registers, although SLEEP
may be automatically entered under certain conditions by appropriate configurations within
Register file: 0x36 – Power Management and System Control. If the UPL_CFG is being set
for a purpose other than going to sleep then needs to be explicitly cleared immediately
after use as it is not self-clearing.
DCA_READ
reg:2C:02
bit:3
Direct AON memory access read. When this bit is set, (and direct access is enabled via the
DCA_ENAB bit below), it commands a direct read of the low-power configuration array
store memory. The address to read from is specified in Sub-Register 0x2C:04 – AON_ADDR
and the resultant read data is presented in Sub-Register 0x2C:03 – AON_RDAT. This access
is needed to retrieve the result of a calibration measurement on the low-power oscillator,
see LPOSC_CAL bit in Sub-Register 0x2C:0A – AON_CFG1.
–
reg:2C:02
bits:6–4
Bits marked ‘-’ in register 0x2C:02 are reserved and should always be written as zero to
avoid any malfunction of the DW1000.
DCA_ENAB
reg:2C:02
bit:7
Direct AON memory access enable bit. This bit needs to be set to 1 to enable the
DCA_READ above to operate. Note: DCA_ENAB must to be reset to 0 to allow the automatic
saving/restoring of user configurations to/from the AON memory, as needed for correct
operation during entry and exit from SLEEP and DEEPSLEEP modes.