to the TX_BUFFER before the DW1000 needed to consume it, then this will be successful and the
frame will be sent with a good CRC, and that is essentially the end of the discussion on this
technique.
If the host system has not been quick enough in writing the data this will result in the frame being
sent with the wrong data but with a bad CRC also. The DW1000 transmitter includes a circuit to
detect the host microprocessor writing to the buffer between the selected TXBOFFS and any address
the IC has already consumed the data from, which is taken to mean that the data is being written
too late for transmission. This “Transmit Buffer Error” condition will cause the DW1000 to ignore the
CANSFCS command so the frame is sent with a bad CRC. It is signalled by the TXBERR bit in Register
file: 0x0F – System Event Status Register. Clearly this is a bad condition that will not help system
performance. It is up to system designers to avoid this condition, debugging and removing it during
the design phase, by ensuring the system responsiveness is sufficient such that this never happens,
(e.g. by employing a faster processor or a faster SPI, or by increasing the response/inter-frame delay
or increasing the preamble length).
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