Denon AVR-3808CI - Page 70

70
AVR-3808CI / AVR-3808 / AVC-3808
18 P82/INT0 SUBBDOWN I-E↓&L EuZ Powerdowndetect(Powerdown:L)
19 P81 IPRST/ O C - - Ed Z IPCONV(FLI2310)reset
20 P80 GUIWRITE O- - - -Z GUIROMrewritecontrol(ACTIVE"L")
21 P77 (GUIRSTSUB)/SUBTDO I - - - - Z (ForGUIRSTfromSUB,Notused)/PLDrewritecontrol(JTAG)
22 P76 MPLDCSMAIN/SUBTMS O C - - Eu Z MAINFPGA(PLD)controlpin/PLDrewritecontrol(JTAG)
23 P75 MPLDDATA/SUBTDI O C - - Eu Z MAINFPGA(PLD)controlpin/PLDrewritecontrol(JTAG)
24 P74 MPLDCLK/SUBTCK O C - - Eu Z MAINFPGA(PLD)controlpin/PLDrewritecontrol(JTAG)
25 P73/CTS2 VIDEOPOWER O C - - Ed Z VIDEOPOWERcontroloutput(H:ON)
26 P72/CLK2 DIGITALPOWER O C - - Ed Z DIGITALPOWERcontroloutput(H:ON)
27 P71/RXD2 VSCL I/O C - - Eu Z
VIDEOI2C-IPCONV(FLI2310)/VENCODER(ADV7320)/VDECODER
(ADV7430)/GUIFPGAcontrolpin
28 P70/TXD2 VSDA I/O C - - Eu Z
VIDEOI2C-IPCONV(FLI2310)/VENCODER(ADV7320)/VDECODER
(ADV7431)/GUIFPGAcontrolpin
29 P67/TXD1 TXD O C - - Eu Z Datatransmissionoutputtooutside
30 P66/RXD1 RXD I - Lv - Eu Z Datareceiveinputfromoutside
31 P65/CLK1 FGAIN O C - - Ed Z FGAINcontrolpin
32 P64/CTS1 CECOUT OC - - EuZ CEC-Dsignaloutputpin(SII9185)
33 P63/TXD0 SOMI O C - - - Z MAIN-SUBμcomcomm.controlpin
34 P62/RXD0 SIMO I - - - Ed Z MAIN-SUBμcomcomm.controlpin
35 P61/CLK0 CLKSIMO I - - - Ed Z MAIN-SUBμcomcomm.controlpin
36 P60/CTS0 REQSOMI O C - - Ed Z MAIN-SUBμcomcomm.controlpin
37 P57 OSR2 O C - - Eu Z A/Dcontrolpin(PCM1804)(48kHz:L)
38 P56 CFSEL0 O C - - Ed Z ENCODERoutputset(480p/576p:H)
39 P55/EPM ADCRST/(FRASHEPM) I/O - Lv - Ed Z ADreset/(Rewritebootstart:Linputset)
40 P54 VSELCLK O C - - - Z GUIbuilt-inVIDEOSWcontrolpin
41 P53 VSELDATA O C - - - Z GUIbuilt-inVIDEOSWcontrolpin
42 P52 VSELC1 O C - - - Z GUIbuilt-inVIDEOSWcontrolpin
43 P51 VSELC2 O C - - - Z GUIbuilt-inVIDEOSWcontrolpin
44 P50/CE CECSEL/(FRASHCE)/DSPBOOT I/O - - - Eu Z
CECoutputLINEswitching/(Rewriteboot:Hinput/DSPbootcontrol
(Rewriteboot:Linput)
45 P47 Z2SSIG.DET I - - - Eu Z ZONE2S-signaldetectinput(H:S-signalinputted)
46 P46 DSPPOWER O - - - - Z SameasDIGITALPOWER(H:ON)
47 P45 (CFSEL1) O C - - - Z Notused(ENCODERoutputset1080i,720P:ZH)
48 P44 HSINT I - E ↓ &L - Ed Z HDMIINSEL(SiI9185)INToutput
49 P43 HDMIRINT I - E ↓ &L - - Z HDMIRECEIVER(SiI9031)INToutput
50 P42 HSCL/EDITSCL I/O C - - Eu Z VIDEOI2C/HDMIEDIT(E2PROM)controlpin
51 P41 HSDA/EDITSDA I/O C - - Eu Z VIDEOI2C/HDMIEDIT(E2PROM)controlpin
52 P40 TMDSSWITCHERRST O C - - Ed Z TMDSSWITCHERHDMIINSEL(SiI9185)reset
53 P37 HDMIRRST O C - - Ed Z HDMIRECEIVER(SiI9135)reset
54 P36 HDMIT1RST O C - - Ed Z HDMITRANSMITTER1(SiI9134)reset
55 P35 HDMIT2RST O C - - Ed Z HDMITRANSMITTER2(SiI9134)reset
56 P34 HDMIT1INT I - Lv - . Z HDMIOUTsignaldetectinput(HDMITRANS1SiI9134)
57 P33 HDMIT2INT I - Lv - - Z HDMIOUTsignaldetectinput(HDMITRANS2SiI9134)
58 P32 DACMDI/ZDACDATA O C - - - Z DACcontrolpin(PCM1791ADBR)/ZONE'sDACcontrolpin(AK4385ET)
59 P31 DACMC/ZDACCLK O C - - - Z DACcontrolpin(PCM1791ADBR)/ZONE'sDACcontrolpin(AK4385ET)
60 VCC VCC - - - - - - +3.3V'
61 P30 DACMS OC - - - Z DACcontrolpin(PCM1791ADBR)
62 VSS VSS - - - - - - GND
63 P27 DACRST O C - - - Z DACcontrolpin(PCM1791ADBR)
64 P26 Z2DACRST O C - - - Z ZONE2'sDACcontrolpin(AK4385ET)
65 P25 Z2DACCS O C - - - Z ZONE2'sDACcontrolpin(AK4385ET)
66 P24 Z3DACCS O C - - - Z ZONE3'sDACcontrolpin(AK4385ET)
67 P23 Z3DACRST O C - - - Z ZONE3'sDACcontrolpin(AK4386ET)
68 P22 V.EXPSTB O C - - - Z STBoutputforvideoexpandercontrol(BU4094BCFV)
69 P21 V.EXPOE O C - - Ed Z OEoutputforvideoexpandercontrol(BU4094BCFV)
70 P20 V.EXPCLK O C - - - Z CLKoutputforvideoexpandercontrol(BU4094BCFV)
71 P17/INT5 V.EXPDIN O C - - - Z DATAoutputforvideoexpandercontrol(BU4094BCFV)
72 P16/INT4 COMPSDET I - Lv - Eu Z MAINZONE'sCOMPONENTsignaldetectinput
73 P15/INT3 Z1VSIG.DET I - Lv - Eu Z MAINZONE'sVIDEOsignaldetectinput(Detected:H)
74 P14/D12 Z1SMONIDET I - - - Eu Z MAINZONE'sS-monitorconnectiondetectinput(Connected:L)
75 P13/D11 Z1SSIG.DET I - - - Eu Z MAINZONE'sS-signaldetectinput(H:S-signalinputted)
76 P12/D10 Z2SYNCDET I - - - Ed Z Sync.detectinputforZONE2OSD(H:Ext.synchronized)
77 P11/D9 DSP1VPP/SUBnCONFIG O C - - Eu - Normal:H,FLASHwriteforDSP:L/FPGArewritecontrol
78 P10/D8 DIR3CKST OC - - EuZ DIRcontrolpin(LC89057W-VF4-E)
79 P07/D7 DIR2CKST OC - - EuZ DIRcontrolpin(LC89057W-VF4-E)
80 P06/D6 PLDWRITE OC - - - Z /PLDrewritecontorol(ACTIVE"L"),JTAGVersionread-outcontrol
81 P05/D5 INT3 I-E↓&L-EdZ DIRcontrolpin(LC89057W-VF4-E)
Pin PinName Symbol I/O Type Det
Op
(Int.)
Op
(Ext.)
Res Function