A109
BAND 2 CONVERTER
(20201 39)
The Band 2 Converter accepts Band 1 and Band 2 RF signals from the front panel, and local oscillator
(LO) signal from the Band 3 Converter
(A203). The appropriate signal
is
selected and processed to produce
an IF signal between 10 Hz and 200 MHz. The IF signal output
is
sent to the Count Chain board (A106),
and lock information
is
routed through the PIA (peripheral interface adapter)
U2 to the Microprocessor
(A105).
IMPEDANCE CONVERTER
Band 1 input from the front panel enters the converter
at
J6 and
is
terminated by R75. The signal is cou-
pled to the input of
a
field effect transistor (FET) amplifier (015) through an RC network (R73, C42).
Two limiter diodes (CR4, CR5) protect the FET against large input signals. The FET
is
a
source follower
with slightly less than unity gain. The FET drives
a
buffer amplifier (Q14) which has enough gain to in-
crease the impedance converter overall gain to near unity. A decoupling capacitor
(C39) controls the
amplifiers low frequency cutoff, and
C41 provides high frequency peaking to keep the gain flat to fre-
quencies above 100 MHz.
SIGNAL SELECT
The output of the impedance converter circuit drives one input of the signal select circuitry. Signal select-
ion
is
made by enabling one of three differential amplifiers, U4A, U4B. or U5A. When Band 1
is
selected,
a
logic high signal on the PIA (U2 pin 2) turns on Q16. Q16 biases on the current source in U4A. This
current source generates an
1 lma current which
is
split between the two differential amplifier transistors
in
U4A. The currents from pins 5 and 6 flow through matched collector loads (R94, L7/R95, L8). R94 and
R95 are equal, and are selected for the proper low frequency gain during board alignment. Inductors
L7
and L8 provide peaking to give an approximate flat gain through 200MHz. Diodes CR9 and CRlO provide
limiting on very strong signals to prevent the next stage from being over driven.
The next stage
is
a
differential amplifier similar to U4A, but
it
is
driven differentially. To generate
a
single
ended output signal, one output of U5B (pin
12)
is
passed through
a
current mirror (018). The output
of the current mirror
is
then added to the second output of U5B (pin 11)
at
J5. The load for this stage
is
a
51 ohm resistor located on the A106 Count Chain board in order to terminate the coax for RF signals.
In the quiescent state, the current from
018 equals the collector current of the differential amplifier U5B,
and the output current
is
zero. When
a
signal
is
applied, the current will be unbalanced to generate
a
signal
at
the load resistor. To provide frequency compensation of the current mirror, an RC network (R108,
C34)
is
connected between the emitter of 018 and ground.
BAND 1 LOCK DETECTOR
The output signal
at
J5
is
coupled to detector CR12. Amplifier U6
is
a
threshold comparator that will
produce
a
logic low signal when the IF output from J5
is
more than -6dBm. The output of U6 goes
through
a
resistor divider network to generate
a
5V TTL logic signal for the PIA. R90 provides about 1 dB
of positive feedback
at
threshold level to prevent eratic output from the comparator.
Scans by ArtekMedia © 2007
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