A1 11
FRONT PANEL LOGIC
(20201 91
)
The Front Panel Logic assembly (A1 11) contains logic circuitry for control of two functions.
DISPLAY CONTROL
KEYBOARD CONTROL
The
+5
V
power supply to the front panel assemblies (A1 10 and A1 11)
is
regulated by
a
voltage
regulator that
is
located behind the A1 11 board. For heatsinking purposes, this voltage regualtor
is
mounted on the chassis. Please refer to figure 11 1 b. Front Panel Logic block diagram on page 11 1-3.
DISPLAY CONTROL
.
-.
The twelve 7-segment LEDs and the three groups of annunciator lights on A1 10 are multiplexed. To
turn on
a
particular segment in
a
digit, both the digit driver for that digit and the segment driver for
that segment must
be
on.
The display logic
is
in constant operation in either the self-scan mode or the memory update mode.
SELF-SCAN MODE
This
is
the normal operating mode. In this mode the display scan clock
is
clocking the display counter
(U6). The state of the display counter determines which digit will be turned on.
The state of the display counter
is
decoded by 4 to 16 line multiplexer (U2), and the appropriate digit
driver
is
turned on. At this time the display memory (U7 and U8)
is
read, and the onloff information
(stored in the display memory for that specific digit), turns the segment drivers
(A110) on or off.
The display intensity
is
controlled by varying the duty cycle of the multiplexing. This
is
done by
varying the resistance of the potentiometer
(R4) which, in turn, varies the length of time the decoder
(U2) and the display memories (U7, U8) are disabled between each scan clock cycle.
At the start of each gate operation the GATE light control
is
triggered, and the GATE LED lights
for the length of the GATE.
MEMORY UPDATE MODE
b
In this mode the multiplexer logic
is
disabled by setting the display scanlupdate control line (PA41
-
to logic 0. The microprocessor controlled clock (clock, PA11
is
used to clock the display counter(U6).
Before updating the display memory (U7 and U8), the display counter
is
cleared by setting the
clearlload control line (PA5) to logic 1, and clocking the clock input of U6.
Update mode timing
is
illustrated in figure 11 la.
Scans by ArtekMedia © 2007
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