A106
COUNT CHAIN
(2020136)
The Count Chain Assembly receives IF signals from the Band 3 IF Amplifier (A201B) and the Band 2 Con-
verter
(A109).
It
also receives a gate signal and a 100 kHz reference signal from the Gate Generator (A107).
The count chain assembly selects the appropriate IF signal, gates
it,
and counts
it
to produce a BCD output
that represents the input frequency.
It
also produces one or two IF output signals to be used for options
at
53 and 54.
The A106 board receives two IF input signals on J1 and J2. The appropriate input
is
selected by enabling
one of two differential amplifiers
(UlA or UlB). Enabling of the appropriate amplifier
is
achieved by
turning on a transistor switch
(Q11 or 012). The appropriate transistor
is
turned on by the output of an
open collector inverter
(U7C or U7A) driven by a TTL signal from the PIA (U10).
The output of the input selector differentially drives a squaring circuit. The squaring circuit consists of a
differentially driven current mirror
(Ql) driving a tunnel diode (CR5). The voltage across the tunnel diode
changes abruptly between two states (approximately
0.2V and 0.5V). The signal across the diode drives the
pulse forming circuit. This circuit begins with a high speed differential amplifier
(Q2 and Q3). The output
of this amplifier drives
Q4 which
is
a current switch. The square wave current, from Q4's collector, drives
an inductor
(Ll). The voltage across the inductor
is
a series of pulses; a positive pulse when Q4 turns on
and a negative pulse when
Q4 turns off. Diode CR5 tends to remove the negative pulses and increases the
damping to improve the amplitude of the positive pulses. The positive pulses from the generator drive a
pulse inverter
((36). The pulse inverter
is
a high-speed zero bias amplifier that
is
biased at cut off by diode
CR6.
'The output of the pulse inverter ((36) drives the input to the first decade counter (U2). The bias for the U2
input
is
established by a tracking bias supply (U3, Q7). The voltage at TP2
is
equal to the voltage on U2 pin
1, plus a fixed DC offset selected by R45. The BCD outputs from U2 are slew-rate limited, and can only be
seen after the counting ends and comes to rest. The carry output on pin 9
is
an ECL level U2 signal, and
is
always visible.
The ECL output of U2 drives an ECL to TTL converter (Q8, Q9 and Q10). This converter
is
a
differential
amplifier with a
cascode output buffer ((28). The response of Q8
is
improved by inductive peaking provided
by L2. The output of
Q8 drives a decade counter (U4) which in turn drives a third decade counter (U5).
The BCD outputs of U4 and U5 are connected to a 6 decade counter (U6) which derives
its
clock infor-
mation directly from the BCD outputs of U5. When counting
is
finished, 8 decades of BCD data are read
by the microprocessor (through the PIA
U10) from U6 by a time multiplex process. Thamultiplexer (set
to the first digit by the end of the previous reset clock) loads the multiplex latches with the Latch Load
clock, and steps to the remaining 7 digits with 7 pulses on the Scan Clock line. The first decade of BCD
data from U2
is
read directly from the PIA.
A single reset line
is
used to reset all count stages to zero before the next count cycle begins.
.
A real-time clock (U8, U9)
is
also on the count chain assembly. This circuit takes the 100kHz reference
signal, that
is
coming from the Counter Interconnect Assembly (AlOO), and divides
it
by 10,000 to give
a
10Hz (100ms) clock. The output from this clock
is
fed to the PIA to allow the microprocessor to gather
time information at a
10Hz rate for timing functions within the program.
Scans by ArtekMedia © 2007
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