Signal Name Frequency Package Pin MPSoC Pin Type
CLK33 33.33 MHz R16 PS_REF_CLK
CLK100_PL_P
100 MHz
AD5 IO_L13P_T2L0Q_GC_64
CLK100_PL_N AD4 IO_L13N_T2L1Q_GC_64
CLK27_GTR_P
27 MHz
A21 PS_MGTREFCLK3P_505
CLK27_GTR_N A22 PS_MGTREFCLK3N_505
CLK100_GTR_P
100 MHz
C21 PS_MGTREFCLK2P_505
CLK100_GTR_N C22 PS_MGTREFCLK2N_505
PS_PADI
32.768 kHz
N17 PS_PADI (crystal pad input for MPSoC built-in RTC)
PS_PADO N18 PS_PADO (crystal pad output for MPSoC built-in RTC)
Table 19: Module Clock Resources
2.13 Reset
The power-on reset signal (POR) and the PS system reset signal (SRST) of the MPSoC device are available
on the module connector.
Pulling PS_POR# low resets the MPSoC device, the Ethernet and the USB PHYs, and the QSPI and eMMC
flash devices. Please refer to the Enclustra Module Pin Connection Guidelines [11] for general rules regarding
the connection of reset pins.
Pulling PS_SRST# low resets the MPSoC device and enables the connection between QSPI flash and module
connector, allowing the flash to be programmed from an external SPI master.
For details on the functions of the PS_POR_B and PS_SRST_B signals refer to the Zynq UltraScale+ MPSoC
Technical Reference Manual [19].
Table 20 presents the available reset signals. Both signals, PS_POR# and PS_SRST#, have on-board 10 kΩ
pull-up resistors to VCC_CFG_MIO. For on-board devices using 1.8 V signaling, a PS_POR# low voltage variant
is generated (PS_POR#_LV).
Signal Name Connector Pin Package Pin FPGA Pin Type Description
PS_POR# A-132 P16 PS_POR_B Power-on reset
PS_SRST# A-124 N19 PS_SRST_B System reset
Table 20: Reset Resources
Please note that PS_POR# is automatically asserted if PWR_GOOD is low.
2.14 LEDs
There are four active-low user LEDs on the Mercury XU5 SoC module - one of them is connected to the PS,
one connected to both PS and PL and two connected to the PL.
D-0000-445-001 36 / 64 Version 07, 25.07.2019
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