Enclustra Mercury XU5 - 2.15 DDR4 SDRAM (PS)

For the LED that can be driven from both PL and PS, it is recommended to drive the FPGA pin to a high
impedance state before driving the PS pin and vice versa.
PS Signal PS Signal PL Signal PL Signal Remarks
Name Location Name Location
LED0#_PS AB19 (MIO24) - - User function/active-low
LED1#_PS AB21 (MIO25) LED1#_PL H2 User function/active-low
- - LED2#_PL P9 User function/active-low
- - LED3#_PL K5 User function/active-low
Table 21: User LEDs
In addition to the user LEDs, two status LEDs are equipped on the module, offering details on the configu-
ration process for debugging purposes.
PS Signal Name PS Signal Location Remarks
PS_ERROR P17 (PS_ERROR_OUT) Refer to Zynq UltraScale+ MPSoC Technical Reference
Manual [19]
PS_STATUS M20 (PS_ERROR_STATUS) Refer to Zynq UltraScale+ MPSoC Technical Reference
Manual [19]
Table 22: Status LEDs
2.15 DDR4 SDRAM (PS)
There are two DDR4 SDRAM channels on the Mercury XU5 SoC module: one attached directly to the PS
side (which is available only as a shared resource to the PL side) and one attached directly to the PL side.
The DDR4 SDRAM connected to the PS is mapped to I/O bank 504. The memory configuration on the
Mercury XU5 SoC module supports ECC error detection and correction; the correction code type used is
single bit error correction and double bit error detection (SEC-DED).
Five 16-bit memory chips are used to build an 72-bit wide memory (8 bits are unused): 64 bits for data and
8 bits for ECC.
Please note that on the smallest module variant (ME-XU5-2CG-1E-D10H) the DDR4 chip for ECC and half of
the DDR4 chips for data are not equipped; in total 2 memory chips are used for the PS DDR4 SDRAM.
The maximum memory bandwidth on the Mercury XU5 SoC module regular variants (full bandwidth) is:
2400 Mbit/sec × 64 bit = 19200 MB/sec
and for the smallest variant (half bandwidth) is:
2400 Mbit/sec × 32 bit = 9600 MB/sec
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