Figure 14: Power-Up Sequence - VCC_IO in Relation with PWR_GOOD and PWR_EN Signals
2.9.6 Signal Terminations
Differential Inputs
Internal differential termination is not supported for the HD pins (banks 24, 25, 44 on ZU2/ZU3 devices, and
banks 45, 44, 43 on ZU4/ZU5 devices). Differential input pairs on the module connector may be terminated
by external termination resistors on the base board (close to the module pins).
Single-Ended Outputs
There are no series termination resistors on the Mercury XU5 SoC module for single-ended outputs. If
required, series termination resistors may be equipped on the base board (close to the module pins).
2.9.7 Multiplexed I/O (MIO) Pins
Details on the MIO/EMIO terminology are available in the Zynq UltraScale+ MPSoC Technical Reference
Manual [19].
Some of the MIO pins on the Mercury XU5 SoC module are connected to on-board peripherals, while others
are available as GPIOs; the suggested functions below are for reference only - always verify your MIO pinout
with the Xilinx device handbook.
Table 10 gives an overview over the MIO pin connections on the Mercury XU5 SoC module. Only the pins
marked with “user functionality” are available on the module connector.
D-0000-445-001 28 / 64 Version 07, 25.07.2019
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