Enclustra Mercury XU5 - 3.2 Pull-Up During Configuration; 3.3 Power-on Reset Delay Override

Warning!
All configuration signals except for BOOT_MODE must be high impedance as soon as the device is
released from reset. Violating this rule may damage the equipped MPSoC device, as well as other
devices on the Mercury XU5 SoC module.
3.2 Pull-Up During Configuration
The Pull-Up During Configuration signal (PUDC) is pulled to GND on the module; as PUDC is an active-low
signal, all FPGA I/Os will have the internal pull-up resistors enabled during device configuration.
If the application requires the pull-up during configuration to be disabled, this can be achieved by removing
R212 component and by mounting R211 - in this configuration the PUDC pin is connected to 1.8 V.
Figure 16 illustrates the configuration of the I/O signals during power-up. Figure 17 indicates the location of
the pull-up/pull-down resistors on the module PCB - middle right part on the bottom view drawing.
Figure 16: Pull-Up During Configuration (PUDC) and Power-on Reset Delay Override (PORSEL)
Figure 17: Pull-Up During Configuration (PUDC) and Power-on Reset Delay Override (PORSEL) Resistors - Assembly
Drawing Bottom View (middle right part)
D-0000-445-001 50 / 64 Version 07, 25.07.2019