Module Variant ME-XU5-2CG/2EG/3EG ME-XU5-4CG/4EV/5EV ME-XU5-4CG/4EV/5EV-G1
Compatibility XU1 (partially) XU1 ZX5 and ZX1-30
Signal Name Pin MPSoC Pin Connectivity
MGTPS_RX3_A26_MGT_
B224_RX3_P1_N
B-44 MGTPS_RX3_A26_N MGTPS_RX3_A26_N MGT_B224_RX3_P1_N
MGT_B224_RX0_Y2_
B65_L11_K4_P
B-48 IO_B65_L11_GC_K4_P MGT_B224_RX0_Y2_P IO_B65_L11_GC_K4_P
MGT_B224_RX0_Y1_
B65_L11_K3_N
B-50 IO_B65_L11_GC_K3_N MGT_B224_RX0_Y1_N IO_B65_L11_GC_K3_N
MGT_B224_RX1_V2_
B65_L3_U8_P
B-54 IO_B65_L3_AD15_U8_P MGT_B224_RX1_V2_P IO_B65_L3_AD15_U8_P
MGT_B224_RX1_V1_
B65_L3_V8_N
B-56 IO_B65_L3_AD15_V8_N MGT_B224_RX1_V1_N IO_B65_L3_AD15_V8_N
MGT_B224_RX2_T2_
B65_L4_R8_P
B-60 IO_B65_L4_AD7_ALERT_R8_P MGT_B224_RX2_T2_P IO_B65_L4_AD7_ALERT_R8_P
MGT_B224_RX2_T1_
B65_L4_T8_N
B-62 IO_B65_L4_AD7_T8_N MGT_B224_RX2_T1_N IO_B65_L4_AD7_T8_N
MGT_B224_RX3_P2_
B65_L5_R7_P
B-66 IO_B65_L5_AD14_R7_P MGT_B224_RX3_P2_P IO_B65_L5_AD14_R7_P
MGT_B224_RX3_P1_
B65_L5_T7_N
B-68 IO_B65_L5_AD14_T7_N MGT_B224_RX3_P1_N IO_B65_L5_AD14_T7_N
IO_BF_L8_HDGC_AD4_
F15_MIO40_P
A-82 IO_BF_L8_HDGC_AD4_F15_P PS_MIO40 IO_BF_L8_HDGC_AD4_F15_P
IO_BF_L8_HDGC_AD4_
E15_MIO41_N
A-84 IO_BF_L8_HDGC_AD4_E15_N PS_MIO41 IO_BF_L8_HDGC_AD4_E15_N
Table 7: Assembly Options for MGT and MIO Signals and Migration Guidelines
2.9.3 Differential I/Os
When using differential pairs, a differential impedance of 100 Ω must be matched on the base board, and
the two nets of a differential pair must have the same length.
The information regarding the length of the signal lines from the MPSoC device to the module connector
is available in Mercury XU5 SoC Module IO Net Length Excel Sheet [3]. This enables the user to match the
total length of the differential pairs on the base board if required by the application.
The I/Os in the HD banks (E, F, N, O) can be used only as differential inputs when LVDS/LVPECL standards
are used; LVDS/LVPECL outputs are not supported.
Internal differential termination is not supported for the HD pins; differential input pairs on the module
connector may be terminated by external termination resistors on the base board (close to the module
pins).
2.9.4 I/O Banks
Table 8 describes the main attributes of the Programmable Logic (PL) and Processing System (PS) I/O banks,
and indicates which peripherals are connected to each I/O bank. All I/O pins within a particular I/O bank
must use the same I/O (VCC_IO) and reference (VREF) voltages.
Bank Connectivity VCC_IO VREF
MGT Bank 224 (available only
on ZU4/ZU5 devices)
Module connector
4
0.9 V -
Continued on next page...
D-0000-445-001 25 / 64 Version 07, 25.07.2019
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