Bank Connectivity VCC_IO VREF
Bank 64 PL DDR4 SDRAM, clock oscilla-
tor
1.2 V 0.6 V
Bank 65
Module connector
4
, LEDs
User selectable User selectable
VCC_IO_B65 0.5 × VCC_IO_B65
Bank 66
Module connector
4
User selectable User selectable
VCC_IO_B66 0.5 × VCC_IO_B66
Bank E Gigabit Ethernet PHY 1, I2C, User selectable
-
25 (ZU2/ZU3) or 45 (ZU4/ZU5) module connector VCC_CFG_MIO
Bank F
Module connector
4
User selectable
-
26 (ZU2/ZU3) or 46 (ZU4/ZU5) VCC_IO_BN
Bank N
Module connector
User selectable
-
24 (ZU2/ZU3) or 44 (ZU4/ZU5) VCC_IO_BN
Bank O
Module connector
User selectable
-
44 (ZU2/ZU3) or 43 (ZU4/ZU5) VCC_IO_BO
PS Bank 503 FPGA PS Configuration
User selectable
-
VCC_CFG_MIO
PS DDR Bank 504 DDR4 SDRAM 1.2 V -
PS Bank 500
eMMC and QSPI flash devices,
1.8 V -
I2C, LEDs
PS Bank 501
Gigabit Ethernet PHY 0, User selectable
-
module connector VCC_CFG_MIO
PS Bank 502 USB PHY 0, USB PHY 1 1.8 V -
PS GTR Bank 505
Module connector
4
, GTR
VCC_PSINT -
oscillators
Table 8: I/O Banks
2.9.5 VCC_IO Usage
The VCC_IO voltages for the I/O banks located on the module connector are configurable by applying the
required voltage to the VCC_IO_B[x], respectively VCC_CFG_[x] pins. All VCC_IO_B[x] or VCC_CFG_[x] pins of
the same bank must be connected to the same voltage. Details on connectivity in I/O banks having generic
names (for example O or N) are presented in Section 2.9.4.
4
Not all I/Os are available on the module connector. Please check the assembly variants description in Section 2.9.2.
D-0000-445-001 26 / 64 Version 07, 25.07.2019