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Enclustra Mercury XU5 - Product Information; Module Configuration

Enclustra Mercury XU5
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Module Product Family Reserved Revision Product Information
Mercury XU5 SoC module 0x0333 0x[XX] 0x[YY] 0x0333 [XX][YY]
Table 43: Product Information
Module Configuration
Addr. Bits Comment Min. Value Max. Value Comment
0x08
7-4 MPSoC type 0 5 See MPSoC type table
(Table 45)
3-0 MPSoC device speed grade 1 3
0x09
7-6 Temperature range 0 2 See temperature
range table (Table 46)
5 Power grade 0 (Normal) 1 (Low power)
4-3 Gigabit Ethernet port count 0 2
2 RTC equipped 0 1
1 Alternative MGT routing
12
0 1
0 DDR4 PS ECC enabled
13
0 (Yes) 1 (No)
0x0A
7-3 Reserved - -
2 DDR4 PS bandwidth
14
0 (Full) 1 (Half)
1-0 USB 2.0 port count 0 2
0x0B
7-4 DDR4 RAM (PS) size (GB) 0 (0 GB) 4 (8 GB) Resolution = 1 GB
3-0 DDR4 RAM (PL) size (MB) 0 (0 MB) 9 (2048 MB) Resolution = 8 MB
0x0C
7-4 eMMC flash size (GB) 0 (0 GB) 5 (16 GB) Resolution = 1 GB
3-0 QSPI flash memory size (MB) 0 (0 MB) 7 (64 MB) Resolution = 1 MB
Table 44: Module Configuration
12 13 14
The memory sizes are defined as Resolution×2
(Value-1)
(e.g. DRAM=0: not equipped, DRAM=1: 1 GB, DRAM=2:
2 GB, DRAM=3: 4 GB, etc).
Table 45 shows the available MPSoC types.
12
This property indicates that the module uses the alternative “G1” MGT routing, as described in Section 2.9.2. For the “G1” assembly
variant, a value of 1 is programmed to the EEPROM. For the other module variants, a value of 0 is programmed to the EEPROM.
13
Property introduced to support the module variants without DDR4 ECC. The new EEPROM map definition is backwards compatible.
14
Property introduced to support the module variants equipped with half of the maximum number of DDR4 chips on the PS side.
The new EEPROM map definition is backwards compatible.
D-0000-445-001 57 / 64 Version 07, 25.07.2019

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