must be connected to GND. The dedicated channel is not available on the module connector.
The analog input signals can be connected to any normal I/O FPGA bank, provided that all analog pins
belong to the same bank. Note that the HD I/O banks have a limited number of analog inputs and they
must be connected directly to the SYSMONE4 primitive instead of to the Xilinx System Management Wizard
IP core.
For detailed information on the ADC and system monitor, refer to the UltraScale Architecture System Monitor
document [20], Zynq UltraScale+ MPSoC Technical Reference Manual [19] and System Management Wizard
Product Guide [22].
Table 11 presents the ADC Parameters for the PL System Monitor. The PS System Monitor is only used for
monitoring the on-chip power supply voltages and die temperature.
Parameter Value (PL Sysmon)
VCC_ADC 1.8 V
VREF_ADC Internal
ADC Range 0-1 V
Sampling Rate per ADC 0.2 MSPS
Total number of channels available on the module connector 16 (only auxiliary inputs)
Table 11: System Monitor (PL) Parameters
2.10 Multi-Gigabit Transceiver (MGT)
There are two types of multi-gigabit transceivers available on the Mercury XU5 SoC module: GTH transceivers
(connected to the PL) and GTR transceivers (connected to the PS). The GTH transceivers are available only
on modules equipped with ZU4/ZU5 MPSoC devices.
GTH Transceivers
On modules equipped with ZU4/ZU5 there are 4 GTH MGTs available on the Mercury XU5 SoC module -
Table 12 describes the connections.
The naming convention for the GTH MGT I/Os is:
MGT_B<BANK>_<FUNCTION>_<P
ACKAGE_PIN>_<POLARITY>.
For example, MGT_B224_TX2_R4_P is located on pin R4 of MGT I/O bank 224, it is a transmit pin and it has
negative polarity.
Signal Name Signal Description Pairs I/O Bank
MGT_B224_RX<...> MGT receivers 4
224
MGT_B224_TX<...> MGT transmitters 4
MGT_B224_REFCLK<...> MGT reference input clocks 2
Total 10
Table 12: MGT Pairs
D-0000-445-001 30 / 64 Version 07, 25.07.2019
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