Chapter 3
ESP32-S2 Hardware Reference
3.1 Chip Series Comparison
The comparison below covers key features of chips supported by ESP-IDF. For the full list of features please refer
to respective datasheets in Section Related Documents.
Table 1: Chip Series Comparison
Feature ESP32 Series ESP32-S2 Series ESP32-C3 Series
Launch year 2016 2020 2020
Variants See ESP32 Datasheet (PDF) See ESP32-S2 Datasheet
(PDF)
See ESP32-C3 Datasheet
(PDF)
Core Xtensa® dual-core 32-bit
LX6 with 600 MIPS (in
total); 200 MIPS for ESP32-
U4WDH/ESP32-S0WD
(single-core variants); 400
MIPS for ESP32-D2WD
Xtensa® single-core 32-bit
LX7 with 300 MIPS
32-bit single-core RISC-V
Wi-Fi proto-
cols
802.11 b/g/n, 2.4 GHz 802.11 b/g/n, 2.4 GHz 802.11 b/g/n, 2.4 GHz
Bluetooth® Bluetooth v4.2 BR/EDR and
Bluetooth Low Energy
✖ Bluetooth 5.0
Typical
frequency
240 MHz (160 MHz for
ESP32-S0WD, ESP32-
D2WD, and ESP32-
U4WDH)
240 MHz 160 MHz
SRAM 520 KB 320 KB 400 KB
ROM 448 KB for booting and core
functions
128 KB for booting and core
functions
384 KB for booting and core
functions
Embedded
flash
2 MB, 4 MB, or none, depend-
ing on variants
2 MB, 4 MB, or none, depend-
ing on variants
4 MB or none, depending on
variants
External
flash
Up to 16 MB device, address
11 MB + 248 KB each time
Up to 1 GB device, address
11.5 MB each time
Up to 16 MB device, address
8 MB each time
External
RAM
Up to 8 MB device, address 4
MB each time
Up to 1 GB device, address
11.5 MB each time
✖
Cache ✓
✓
✓ Two-way set associative ✓
✓
✓ Four-way set associative,
independent instruction cache
and data cache
✓
✓
✓ Eight-way set associa-
tive, 32-bit data/instruction
bus width
Peripherals
ADC Two 12-bit, 18 channels Two 13-bit, 20 channels Two 12-bit SAR ADCs, at
most 6 channels
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