Chapter 2. API Reference
I2C_ADDR_BIT_10
I2C 10bit address for slave mode
I2C_ADDR_BIT_MAX
enum i2c_ack_type_t
Values:
I2C_MASTER_ACK = 0x0
I2C ack for each byte read
I2C_MASTER_NACK = 0x1
I2C nack for each byte read
I2C_MASTER_LAST_NACK = 0x2
I2C nack for the last byte
I2C_MASTER_ACK_MAX
enum i2c_sclk_t
I2C clock source, sorting from smallest to largest, place them in order. This can be expanded in the future use.
Values:
I2C_SCLK_DEFAULT = 0
I2C source clock not selected
I2C_SCLK_APB
I2C source clock from APB, 80M
I2C_SCLK_REF_TICK
I2C source clock from REF_TICK, 1M
I2C_SCLK_MAX
2.2.9 Inter-IC Sound (I2S)
Overview
I2S (Inter-IC Sound) is a serial, synchronous communication protocol that is usually used for transmitting audio data
between two digital audio devices.
ESP32-S2 contains one I2S peripheral(s). These peripherals can be configured to input and output sample data via
the I2S driver.
An I2S bus consists of the following lines:
• Master clock line (operational)
• Bit clock line
• Channel select line
• Serial data line
Each I2S controller has the following features that can be configured using the I2S driver:
• Operation as system master or slave
• Capable of acting as transmitter or receiver
• DMA controller that allows for streaming sample data without requiring the CPU to copy each data sample
Each controller can operate in half-duplex communication mode. Thus, the two controllers can be combined to
establish full-duplex communication.
The I2S peripherals also support LCD mode for communicating data over a parallel bus, as used by some LCD
displays and camera modules. LCD mode has the following operational modes:
• LCD master transmitting mode
• Camera slave receiving mode
• ADC/DAC mode
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