Espressif ESP32-S2 User Manual

Chapter 4. API Guides
extern const uint8_t bin_start[] asm("_binary_ulp_app_name_bin_start");
extern const uint8_t bin_end[] asm("_binary_ulp_app_name_bin_end");
void start_ulp_program() {
ESP_ERROR_CHECK( ulp_riscv_load_binary( bin_start,
(bin_end - bin_start)) );
}
esp_err_t ulp_riscv_load_binary(const uint8_t *program_binary, size_t program_size_bytes)
Load ULP-RISC-V program binary into RTC memory.
Different than ULP FSM, the binary program has no special format, it is the ELF file generated by RISC-V
toolchain converted to binary format using objcopy.
Linker script in components/ulp/ld/esp32s2.ulp.riscv.ld produces ELF files which correspond to this format.
This linker script produces binaries with load_addr == 0.
Return
• ESP_OK on success
• ESP_ERR_INVALID_SIZE if program_size_bytes is more than 8KiB
Parameters
• program_binary: pointer to program binary
• program_size_bytes: size of the program binary
Once the program is loaded into RTC memory, the application can start it, calling the ulp_riscv_run() function
ESP_ERROR_CHECK( ulp_riscv_run() );
esp_err_t ulp_riscv_run(void)
Run the program loaded into RTC memory.
Return ESP_OK on success
4.29.5 ULP-RISC-V Program Flow
The ULP-RISC-V coprocessor is started by a timer. The timer is started once ulp_riscv_run() is called.
The timer counts the number of RTC_SLOW_CLK ticks (by default, produced by an internal 90kHz RC oscilla-
tor). The number of ticks is set using RTC_CNTL_ULP_CP_TIMER_1_REG register. When starting the ULP,
RTC_CNTL_ULP_CP_TIMER_1_REG will be used to set the number of timer ticks.
The application can set ULP timer period values (RTC_CNTL_ULP_CP_TIMER_1_REG) using the
ulp_set_wakeup_period() function.
Once the timer counts the number of ticks set in the RTC_CNTL_ULP_CP_TIMER_1_REG register, the ULP
coprocessor will power up and start running the program from the entry point set in the call to ulp_riscv_run().
The program runs until the field RTC_CNTL_COCPU_DONE in register RTC_CNTL_COCPU_CTRL_REG gets
written or when a trap occurs due to illegal processor state. Once the program halts, the ULP coprocessor will power
down, and the timer will be started again.
To disable the timer (effectively preventing the ULP program from running again), please clear the
RTC_CNTL_ULP_CP_SLP_TIMER_EN bit in the RTC_CNTL_STATE0_REG register. This can be done both
from the ULP code and from the main program.
4.30 Unit Testing in ESP32-S2
ESP-IDF provides the following methods to test software.
Espressif Systems 1502
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Release v4.4

Espressif ESP32-S2 Specifications

General

Brand	Espressif
Model	ESP32-S2
Category	Single board computers
Language	English