Espressif ESP32-S2 User Manual

Chapter 4. API Guides
set VARIABLE_NAME value
To set a variable from the command line (replace the name of .cfg file with the correct file for your board):
openocd -c 'set VARIABLE_NAME value' -f board/esp-xxxxx-kit.cfg
It is important to set the variable before including the ESP-specific configuration file, otherwise the variable will not
have effect. You can set multiple variables by repeating the -c option.
Table 6: Common ESP-related OpenOCD variables
Variable Description
ESP_RTOS Set to none to disable RTOS support. In this case, thread list will not be available
in GDB. Can be useful when debugging FreeRTOS itself, and stepping through the
scheduler code.
ESP_FLASH_SIZE Set to 0 to disable Flash breakpoints support.
ESP_SEMIHOST_BASEDIRSet to the path (on the host) which will be the default directory for semihosting func-
tions.
How debugger resets ESP32-S2? The board can be reset by entering mon reset or mon reset halt into
GDB.
Do not use JTAG pins for something else Operation of JTAG may be disturbed, if some other h/w is connected
to JTAG pins besides ESP32-S2 module and JTAG adapter. ESP32-S2 JTAG is using the following pins:
Table 7: ESP32-S2 pins and JTAG signals
ESP32-S2 Pin JTAG Signal
MTDO / GPIO40 TDO
MTDI / GPIO41 TDI
MTCK / GPIO39 TCK
MTMS / GPIO42 TMS
JTAG communication will likely fail, if configuration of JTAG pins is changed by user application. If OpenOCD
initializes correctly (detects the two Tensilica cores), but loses sync and spews out a lot of DTR/DIR errors when the
program is ran, it is likely that the application reconfigures the JTAG pins to something else, or the user forgot to
connect Vtar to a JTAG adapter that needed it.
Below is an excerpt from series of errors reported by GDB after the application stepped into the code that reconfigured
MTDO pin to be an input:
cpu0: xtensa_resume (line 431): DSR (FFFFFFFF) indicates target still busy!
cpu0: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated␣
,→an exception!
cpu0: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated␣
,→an overrun!
cpu1: xtensa_resume (line 431): DSR (FFFFFFFF) indicates target still busy!
cpu1: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated␣
,→an exception!
cpu1: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated␣
,→an overrun!
JTAG with Flash Encryption or Secure Boot By default, enabling Flash Encryption and/or Secure Boot will
disable JTAG debugging. On first boot, the bootloader will burn an eFuse bit to permanently disable JTAG at the
same time it enables the other features.
Espressif Systems 1385
Submit Document Feedback
Release v4.4

Espressif ESP32-S2 Specifications

General

Brand	Espressif
Model	ESP32-S2
Category	Single board computers
Language	English