Chapter 2. API Reference
Public Members
bool use_apll
true: use APLL clock; false: use APB clock.
uint32_t div_num
Division factor. Range: 0 ~ 255. Note: When a higher frequency clock is used (the division factor is less
than 9), the ADC reading value will be slightly offset.
uint32_t div_b
Division factor. Range: 1 ~ 63.
uint32_t div_a
Division factor. Range: 0 ~ 63.
Macros
ADC_ARBITER_CONFIG_DEFAULT()
ADC arbiter default configuration.
Note ESP32S2: Only ADC2 supports (needs) an arbiter.
Enumerations
enum adc_unit_t
ADC unit enumeration.
Note For ADC digital controller (DMA mode), ESP32 doesn’t support ADC_UNIT_2, ADC_UNIT_BOTH,
ADC_UNIT_ALTER.
Values:
ADC_UNIT_1 = 1
SAR ADC 1.
ADC_UNIT_2 = 2
SAR ADC 2.
ADC_UNIT_BOTH = 3
SAR ADC 1 and 2.
ADC_UNIT_ALTER = 7
SAR ADC 1 and 2 alternative mode.
ADC_UNIT_MAX
enum adc_channel_t
ADC channels handle. See adc1_channel_t, adc2_channel_t.
Note For ESP32 ADC1, don’t use ADC_CHANNEL_8, ADC_CHANNEL_9. See adc1_channel_t.
Values:
ADC_CHANNEL_0 = 0
ADC channel
ADC_CHANNEL_1
ADC channel
ADC_CHANNEL_2
ADC channel
ADC_CHANNEL_3
ADC channel
ADC_CHANNEL_4
ADC channel
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