Espressif ESP32-S2 User Manual

Chapter 2. API Reference
Term Definition
Host The SPI controller peripheral external to ESP32-S2 that
initiates SPI transmissions over the bus, and acts as an
SPI Master.
Device SPI slave device (general purpose SPI controller). Each
Device shares the MOSI, MISO and SCLK signals but
is only active on the bus when the Host asserts the De-
vice’s individual CS line.
Bus A signal bus, common to all Devices connected to one
Host. In general, a bus includes the following lines:
MISO, MOSI, SCLK, one or more CS lines, and, op-
tionally, QUADWP and QUADHD. So Devices are
connected to the same lines, with the exception that
each Device has its own CS line. Several Devices can
also share one CS line if connected in the daisy-chain
manner.
• MISO
Master In, Slave Out, a.k.a. Q. Data transmission from
a Device to Host.
• MOSI
Master Out, Slave in, a.k.a. D. Data transmission from
a Host to Device.
• SCLK
Serial Clock. Oscillating signal generated by a Host that
keeps the transmission of data bits in sync.
• CS
Chip Select. Allows a Host to select individual De-
vice(s) connected to the bus in order to send or receive
data.
• QUADWP
Write Protect signal. Only used for 4-bit (qio/qout)
transactions.
• QUADHD
Hold signal. Only used for 4-bit (qio/qout) transactions.
• Assertion
The action of activating a line. The opposite action of
returning the line back to inactive (back to idle) is called
de-assertion.
Transaction One instance of a Host asserting a CS line, transferring
data to and from a Device, and de-asserting the CS line.
Transactions are atomic, which means they can never be
interrupted by another transaction.
Launch edge Edge of the clock at which the source register launches
the signal onto the line.
Latch edge Edge of the clock at which the destination register
latches in the signal.
Driver Features
The SPI slave driver allows using the SPI peripherals as full-duplex Devices. The driver can send/receive transactions
up to 72 bytes in length, or utilize DMA to send/receive longer transactions. However, there are some known issues
related to DMA.
SPI Transactions
A full-duplex SPI transaction begins when the Host asserts the CS line and starts sending out clock pulses on the
SCLK line. Every clock pulse, a data bit is shifted from the Host to the Device on the MOSI line and back on the
MISO line at the same time. At the end of the transaction, the Host de-asserts the CS line.
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Espressif ESP32-S2 Specifications

General

Brand	Espressif
Model	ESP32-S2
Category	Single board computers
Language	English