Section 6B
Digital Controller
DIGITAL CONTROLLER BLOCK DIAGRAM 6B-1.
The A13 Controller PCA, under the direction of the instrument software, handles the
data interface between the front panel, remote interface, and 6080A/AN functions.
The controller is located in a top side compartment of the lower module section.
The controller consists of the following functional groups:
Microprocessor
Memory
Front Panel Interface
IEEE-488 Interface
Attenuator Control Interface
Module I/O Interface
Status and Control Latches
Refer to Figure 6B-1 to identify the major sections and trace signal paths.
DIGITAL CONTROLLER CIRCUIT DESCRIPTION (A13) 6B-2.
Microprocessor 6B-3.
The software is executed on a 68HCOOO 16-bit microprocessor. The 8-MHz digital
system clock signal is generated by an oscillator comprised of gates from U18 and
crystal Yl.
Supply voltage monitor TL7705A (U13) generates the active low reset signal to the
68HC000. The reset signal is generated on power-up or if the +5V supply drops below
+4.5V. The reset signal remains low for 200 ms.
Memory 6B-4.
The program instructions and constant data are stored in two 128-KB EPROMs, U2
and U3. The stack and program variables are stored in two 8-KB static RAMs U6 and
U7. Non-volatile front panel setups, and one half of the redundant calibration/
compensation memory are contained in the battery-backed CMOS RAM U8. The
other half of the redundant calibration/compensation memory is contained in the
EEPROM U9.
The rear panel CAL|COMP switch protects the calibration/compensation memory
from accidental destruction.
6B-1
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