TROUBLESHOOTING AND REPAIR
FREQUENCY SYNTHESIS
LOOP AMPLIFIER
The loop amplifier-integrator consists of operational amplifier U34, C98, and R44.
Capacitors C97 and C102 filter the 1-MHz reference. The output of the integrator is
connected to a multi-pole LC filter (R45, C104, C105, C106, C107, L56, L57, and R48)
that attenuates the delete rate (10 and 20 kHz), and reference 1-MHz spurs.
Diodes CR12, CR13, CR14, CR15, CR22 and CR23 speedup the loop during
switching. Additional lead/lag compensation is provided by C114, C115, R58, and
R59. The second lead/lag network is switched by Q10 when the VCO frequency is
above 230 MHz. This is necessary to compensate for the wide Kv range of the VCO.
Amplifier U35 is a precision clamp to keep the VCO frequency within a specified range.
The photoisolator U36 detects when the clamp is active, indicating an out-of-lock
condition. This signal is sent to the controller as the SUBUNLKL status.
LOW ORDER DIGITS GENERATOR
The low order digits generator consists of the clock generator (U21, U22, Q1, Q2), the
gate array U23, the divide-by-1000 (U60, U61), the low-pass filter (L75, L76), and the
active quadrature generator, U59. Internal to the gate-array U23 is a 3 ½ decade-rate
multiplier, associated latches, and a divide-by-2.
The 40-MHz reference from the Coarse Loop is converted to ECL in U20 and then
converted to TTL in Ql and Q2. This is followed by a 20-MHz two-phase clock
generator U21, U22.
The input frequency to the rate multiplier is 20 MHz. The output frequency can be
programmed from zero to 19.995 MHz in 5-kHz steps. This signal is ORd with the
other phase of the 20-MHz clock to produce 20 to 39.995 MHz at U23 pin 1. The signal
is also divided by 2 in U23, by 10 in U60, and again by 100 in U61 to produce 10 to
19.99975 kHz in 2.5-Hz steps. Not all of this resolution is utilized. This TTL signal at
TP30 is filtered by L75, L76, C156, C157, C158, C159, and C160. Op-amp U59 forms
an active quadrature generator such that the signal at output pins 7 and 14 are offset by
90 degrees. These two signals are the 10- to 20-kHz inputs for the PLL single-sideband
mixer.
DACS AND LATCHES
The control bits for the Coarse Loop PCA are latched by U3, part of U9 and U10.
DAC U5 with op-amp U6D provides the steering voltage for the Coarse Loop VCO
and DAC U7B with op-amp U6B provides the voltage to tune the reference TXCO.
SUB-SYNTHESIZER TROUBLESHOOTING 6C-4.
NOTE
AII frequencies mentioned are synthesized; hence they are exact (coherent
with the 10-MHz reference), unless noted as approximate.
Status code 242 indicates that the Sub-Synthesizer and/or Sub-Synthesizer VCO is
not functioning properly. This status code is triggered when the Sub-Synthesizer VCO
control voltage is out of the normal operating range. A status code 244, which indicates
that the Sum Loop is out of lock, might also indicate a problem with the
Sub-Synthesizer and/or Sub-Synthesizer VCO.
6C-9
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