TROUBLESHOOTING AND REPAIR
FREQUENCY SYNTHESIS
Each oscillator uses a common-base transistor (Q4) configured for negative resistance
at the emitter. The emitter is coupled to a resonator that consists of a printed
transmission line in series with varactor diodes (CR7, CR8) and low loss porcelain
capacitors (C7, C8). Two tuning voltage lines connect to the varactor cathodes and
anodes via RF chokes L8 and L4, respectively. The cathode lines connect to the VCO
steering port, J5. The anode lines connect to the VCO phase lock port, J6. These ports
are used by the A12 Sum Loop PCA to control the operating frequency. The voltage
across the varactors, measured between J6 and J5, varies approximately linearly with
frequency in each band, from about +2V to +20V.
The +13 dBm nominal signal at the oscillator transistor collector is applied to an 8-dB
attenuator that provides isolation (R18-R20), and then to a low-pass filter that
attenuates harmonics to less than -20 dBc (C51, C52 and printed lines). PIN diode
CR12 has low RF resistance and passes the oscillator signal when the oscillator is on,
and goes to a high impedance when the oscillator is off.
Band control signals SUMVCO0H and SUMVCO1H are decoded by U5 and Q5-Q10.
This circuit applies bias current only to the selected oscillator transistor. Thus, only
one oscillator is activated per band.
PIN diodes CR9-CR12 connect the active oscillator to a resistive signal splitter (R22,
R23, R50). One signal splitter output goes to series-connected monolithic 11-dB
amplifiers U1 and U2. A -12 dB pad (R26-R28) is between U1 and U2. Two amplifiers
are required for adequate isolation between the Sum Loop and the Premodulator
assemblies. The output of U2, at about +7 dBm, is connected to the A10 Premodulator
PCA by a plug in capacitor at J7.
The other signal splitter output goes to an identically configured circuit including
amplifiers U3 and U4. Following U4 is a low pass filter including C69 and C70 that
attenuates high frequency harmonics. The filtered output from U4 is connected to the
A12 Sum Loop PCA at P1 by a through-the-plate composition resistor. This
component behaves as a distributed RC lowpass filter at very high frequencies, and
improves sum loop spurious performance.
SUM LOOP VCO TROUBLESHOOTING 6C-40.
The Sum Loop VCO PCA, along with the Sum Loop PCA, generates the fundamental
frequency band. A problem with the Sum Loop VCO can cause Sum Loop Unlock
status code 244 or Sum Loop Unlevel status code 245 to appear. Self-Test error codes
327 through 333 can also be triggered by a faulty Sum Loop VCO. To determine that
the Sum Loop VCO is faulty, rather than another assembly, the following tests can be
performed.
1. Ground the phase lock port of the VCO with a clip lead (J6, Sum Loop VCO or
TP4, Sum Loop).
2. Measure the DC voltage at J5 with the signal generator programmed to SPCL 943
(All DACs to full scale).
The reading should be +26.00V.
3. Program the UUT to SPCL 942 (All DACs to half scale).
The reading should be +13.00V. This tests the VCO steering voltage circuit.
6C-45
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