TROUBLESHOOTING AND REPAIR
FREQUENCY SYNTHESIS
The Sum Loop VCO signal at J9 is applied to buffer amplifiers U7 and U8. PIN diode
CR4 follows U8 and acts as an adjustable attenuator to control the level at the RF port
of double balanced mixer U1. A low-pass filter including C81 and C82 precedes U1 RF
port and attenuates high order harmonics in the RF signal. The LO port of U1 is driven
by a two-stage amplifier that includes Q1 and Q2. This amplifier accepts the +7 dBm
signal from the Coarse Loop VCO at J11 and produces +20 dBm of drive power at the
LO port of U1.
U1 generates the IF1 signal at the IF port. This signal is filtered by a 10-element,
100-MHz low-pass filter with input at L3 and output at C27. The filter is contained
within a channel in an aluminum cover piece that improves high frequency
attenuation. This cover also shields the IF1 amplifiers and the IF2 low-pass filter. The
-14-dBm IF1 signal at the filter output is amplified by Q5, configured for 21-dB gain.
Q5 drives level detector diode CR1 at +7 dBm. CR1, U4 and associated components
form a level control loop that holds RF level constant at CR1 by adjusting modulator
PIN diode CR4 bias current. This action also holds the signal level at U1 RF port to a
constant value. Accurate RF port level control is necessary to control mixer intermod
spurs and noise floor. The leveled IF1 signal at CR1 is next applied to a 6-dB
attenuator (R25-27) and then to Q6, which is configured as a 20-dB amplifier. Q6
drives the LO port of double balanced mixer U2 with about +20 dBm. The 80-MHz
signal from the A14 FM PCA is applied to the RF port of U2. This signal is coupled via
a capacitor at J17. Q8 and associated components buffer and low-pass filter this signal,
which is then applied to U2 at a level of -8 dBm.
U2 generates the IF2 signal at the IF port. This signal is filtered by a nine-element,
20-MHz low-pass filter with input at L9 and output at L23. Like the IF1 filter, this
filter is contained within a channel in an aluminum cover piece that improves high
frequency attenuation. The -14 dBm signal at the filter output drives the IF2 amplifier,
which includes Q9 and Q10 and is configured for 21 dB gain. Q10 drives the RF port of
mixer U3 with +7 dBm, which is used as a phase detector. The IF2 low-pass filter also
provides a DC path for +15V power for the IF2 amplifier.
The LO port of phase detector U3 is driven by a signal derived from the
Sub-Synthesizer PCA, as follows. J10 is connected to the 16- to 32-MHz signal from
the A3 Sub-Synthesizer PCA. This ECL level signal is converted to TTL by Q11 and
related parts. The TTL signal then drives U5, a D type flip-flop that is configured to
halve the input frequency. The resulting 8-to 16-MHz Q and Q (compliment) outputs
of U5 drive the LO port of U3. The IF output of U3 drives the loop filter, a 13-element
low-pass type with input at R56 and output at L26. This filter allows audio frequency
components to pass with minimum phase shift while adequately attenuating RF mixer
products. The loop filter output voltage is proportional to the phase difference
between the RF and LO ports of U3. This signal drives the Audio Section, which is
described in the following paragraphs.
Audio Section 6C-31.
The Audio Section contains the circuits required to acquire and maintain phase lock.
Inputs to this section include the phase detector voltage, Sum Loop VCO coarse
steering voltage (SUMSTEER), FM modulation signal (SUMAUDIO), FM range
switching signals (SUMVCO4-6), and Sum Loop VCO Kv information
(SUMCOMPHO-7). Audio Section outputs include Sum Loop VCO steering port and
phase lock port voltages, and a phase lock status indicator for the controller. These
circuits are described in the following paragraphs.
6C-35
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