Section 6C
Frequency Synthesis
FREQUENCY FAULT TREE 6C-1.
The Frequency Synthesis Fault Tree, Figure 6C-1, is the starting point for trouble-
shooting frequency-related problems.
SUB-SYNTHESIZER BLOCK DIAGRAM 6C-2.
Refer to the Sub-Synthesizer Block Diagram (Figure 6C-2) to identify the major
functional blocks and follow the signal paths of the Sub-Synthesizer.
SUB-SYNTHESIZER CIRCUIT DESCRIPTION (A4) 6C-3.
The Sub-Synthesizer PCA (A4), in conjunction with the Sub-Synthesizer VCO PCA
(A3) generates a 16- to 32- MHz signal in 2-Hz steps. This board also distributes power,
control lines, and programmable DC voltages to the Coarse Loop PCA (A2). Status
lines from the Coarse Loop PCA back to the Controller PCA (A13) are also routed
through this board.
The Sub-Synthesizer phase-lock loop (PLL) is a fractional divider PLL with a
single-sideband (SSB) mixer in the feedback path. The oscillator for this loop is a
separate PCA, the A3 Sub-Synthesizer VCO PCA. The VCO frequency is 160 to 320
MHz. A 10/1 divider on the VCO PCA produces the 16- to 32-MHz signal.
The key signals to the PLL are the 1-MHz reference signal from the 40-MHz reference
circuit, the 160- to 320-MHz signal from the VCO, and the 10- to 20-kHz signal from
the low order digit generator circuit. The fractional division technique provides
provides 10-kHz frequency resolution at the VCO frequency (160 to 320 MHz).
The SSB mixer, in conjunction with the low order digit generator provides an
additional 20-Hz resolution at the VCO frequency.
6C-1
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