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Fluke 6080A - COARSE LOOP CIRCUIT DESCRIPTION (A2) 6 C-13.; REFERENCE SECTION BLOCK DIAGRAM 6 C-14.

Fluke 6080A
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TROUBLESHOOTING AND REPAIR
FREQUENCY SYNTHESIS
Table 6C-2. A3 Sub-Synthesizer VCO PCA DC Voltages
COARSE LOOP CIRCUIT DESCRIPTION (A2) 6C-13.
The Coarse Loop PCA generates frequencies from 576 to 960 MHz in 8-MHz steps. It
also provides a 40-MHz reference for the Sub-Synthesizer, a 20-MHz signal for the
modulation oscillator, and an 80-MHz signal for the output section. This 80-MHz
signal is the local oscillator signal for the heterodyne band and is the reference for the
FM circuitry.
The board can be broken down into two major blocks: the reference section and the
coarse loop itself.
REFERENCE SECTION BLOCK DIAGRAM 6C-14.
Refer to the Reference Section Block Diagram (Figure 6C-6) and the schematic
(Section 8) to identify the major functional sections and follow the signal paths of the
coarse loop reference section.
The reference section is a phase lock loop in which the VCO is a 40-MHz voltage
controlled crystal oscillator, a divide-by-4, by-8, by-20, by-40, a digital phase
frequency detector, and associated logic.
The main reference for the instrument is either a 10-MHz temperature controlled
crystal oscillator (TCXO) (U501), or an external 1-, 2-, 5-, or 10-MHz signal.
When the instrument is set to internal reference (EXTREFH=0), the TXCO is turned
on by enabling Q501 via an open-collector comparator (U509C) and associated logic
(U502, U514). The 10 MHz from the TCXO is routed through U502 to a multiplexer
(U504B). The output of the multiplexer is connected to the reference input of the phase
detector (U503A, U511D).
When the instrument is set to external reference (EXTREF=1), the TCXO is turned
off. The external signal from J6 is attenuated (R521-523), clipped (CR501-2), and
high-passed (C524-5, L502). High-speed comparator (U510) converts the external
reference signal to TTL. The output of U510 is connected to the other input of a
multiplexer (U504B). A portion of the comparator output is fed back to the input to
provide hysteresis (R524-7).
6C-17
LOCATION
Q1 collector
Q2 collector
U1 output
CR5/CR7/R10 node, V(phaselock) ~< 7.5V
CR5/CR7/R10 node, V(phaselock) ~> 7.5V
U2 output
U3 pin 2
VOLT DC
+8.7
+7.1
+3.9
+2.3
-2.3
+4.4
+3.5

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