TROUBLESHOOTING AND REPAIR
FREQUENCY SYNTHESIS
C644), amplified (Q610), and filtered again (C649, C50, L613, L615). This is the
80-MHz signal to the output section (J5). When in the DCFM mode and not in the
heterodyne band, this signal is turned off (Q611) via REF80H.
COARSE LOOP BLOCK DIAGRAM 6C-15.
Refer to the Coarse Loop Block Diagram (Figure 6C-7) and the schematic (Section 8)
to identify the major functional sections and follow the signal paths of the coarse loop.
The coarse loop consists of two interlocking loops: the main phase lock loop and the
discriminator loop around the VCO. (The discriminator loop reduces the phase noise
of the
VCO.)
The 576- to 960-MHz signal from the Coarse Loop VCO (A5) (P2) is attenuated
(R401-403), amplified (U401), attenuated again (R407-409) and amplified again
(U405). This signal drives a divide-by-4 pre-scaler (U301). The output of the pre-scaler
(144 to 240 MHz) is amplified (U311) to ECL levels.
The main N-divider consists of two parts: a programmable divide by 3/4/5/6/7 (U302,
U303, U308, U310), and a programmable 5-bit rate multiplier (U304, U305, U306,
U307). The divide by 3/4/5/6/7 is a ring counter with different feedback paths selected
to change the division. It is programmed with the CF0/CF1 bits to a steady-state value
of N= 3,4,5, or 6. A toggle line (TP2) allows the divider to be programmed to one more
than its steady-state value (N+l). The rate multiplier generates a sequence of 0 to 19
pulses within a 40-MHz frame. The output of the rate multiplier drives this toggle line.
Consequently, the divider divides by N part of the frame and N+1 for the remainder of
the frame. Depending on how the rate multiplier is programmed, fractional division
with a 2-MHz step size is obtained. Because of the divide by 4 pre-scaler, this
corresponds to a 8-MHz step at the Coarse Loop VCO frequency.
The output of the N-divider (U308-15,9) is connected to the mixer phase detector
(U203). The 40 MHz from the reference section is buffered in a common base stage
(Q205) and amplified (Q206) to provide the other input to the phase detector. The
output of the phase detector is low-pass filtered (C212-16, L204-5) with notches at 2
and 4 MHz to suppress the rate multiplier spurs. A lead-lag network (R210-11, C211)
provides proper high-frequency termination for the mixer. The output of the filter is
connected to a loop amplifier (U205). This amplifier provides lead-lag compensation
for the phase lock loop. The output of this stage is fed into the acquisition oscillator
state (U206). This is set up as a Wien bridge oscillator (R225-28, C228-29) at a
frequency of approximately 100 Hz. Since the phase detector is not a phase/frequency
detector, the beat frequency at the output of the phase detector must be small in order
for the loop to lock. When the loop is unlocked, the Wien bridge oscillator is
oscillating, and the VCO frequency is slowly swept about its steered frequency. This
causes the beat frequency to be slowly swept close to 0. When the loop locks, there is
enough gain around the loop so the oscillation condition for the Wien bridge is no
longer met and it stops oscillating. A one-shot (U204) is tripped when the Wien bridge
is oscillating, which indicates an out-of-lock condition. This signal (CORUNLKL) is
sent to the controller. The output of the acquisition oscillator is fed into a
programmable lead-lag network (R229-237, C231-235, Q201-204). Since the tuning
slope of the VCO, in MHz/V, is not constant, this network is programmed to reduce
the magnitude of the change. The output of this network is connected to the phaselock
port of the Coarse Loop VCO (J4). This network forms part of the compensation of the
discriminator loop. A comparator (U208) converts the TTL programming input to
0/10V to drive the FETs. Another comparator (U210) monitors the phaselock voltage.
It generates signals when the voltage exceeds -5V (CORVOLH) or +5V (CORVOLL).
This is used for the Coarse Loop VCO compensation.
6C-20
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