TROUBLESHOOTING AND REPAIR
DIGITAL CONTROLLER
Under normal operation, a front panel interrupt should be generated every 540 μs at
pin 6 of U21. If the display has been turned off by special function, there should be an
interrupt generated every 16.3 ms. Verify the divided outputs from U14 and U20 and
make sure that a reset signal at U21 pin 1 is generated after each interrupt.
Verify that the IEEE-488 Interface interrupt signal, IEINTL, is in the inactive (high)
state. If IEINTL is active, make sure the microprocessor kernel and buses are
operating correctly since the software must be operating before the IEEE interrupt can
be initialized properly. Next, troubleshoot communications with the IEEE-488
interface IC using the diagnostic tests under the heading "I/O Diagnostic Tests" later in
Section 6B.
Microprocessor Bus 6B-19.
The dynamic nature of the microprocessor bus makes it difficult to verify the data
transmitted at any given time. However, most common bus faults show recognizable
symptoms and can be found with the aid of the address bus diagnostic test.
To initiate the bus diagnostic test, turn off the instrument power and set DIP switches
2, 3, and 4 of S1 to the on position. Remove U11 from its socket to disable all memory
and I/O chip selects, then turn the power on. This test generates predictable activity on
the control signals and the address bus.
Look at the bus control signals (AS, R/W, UDS, LDS) with an oscilloscope. Suspect
inactive signals or signals that enter invalid logic states. Also compare the inputs and
outputs of gated signals.
All the address bus signals should have square waves of varying frequencies. The
least-significant signal (A1) has the highest frequency, and successively higher order
signals have a frequency half that of the previous line. Note that there are small glitches
on all of the address signals during the low cycle. These are normal and are not really
glitches. The address lines are momentarily tri-stated between bus cycles, and the
pull-up resistors only pull the signals part way up before the next bus cycle begins.
If the microprocessor bus test does not function as described, suspect the micro-
processor kernel and the data bus. Check for data lines shorted together or shorted to
the power supply. Also look for ICs that may be driving the data bus
If the control and address signals appear normal, set the DIP switches to the off
position and install U11.
Address Decoder 6B-20.
Several levels of address decoding are used to select the memory and I/O devices.
Figure 6B-2 shows the levels of decoding.
Decoder PAL U11 generates the major memory segment selects. Verify that all of its
address and control inputs are working properly. The signal CMWRL is the
write-protection signal for the calibration/compensation memory. Signal CMWRL is
tied directly to the rear panel CAL|COMP switch. Signals NVWR and COMPWR are
software controlled write-protection signals for the non-volatile memory and the
calibration/compensation memory, respectively.
6B-6
To Next Page
Loading...
