TROUBLESHOOTING AND REPAIR
FREQUENCY AND PHASE MODULATION
The circuits of Q3 and Q4 provide clean power supply voltages of nominal +14V DC
and -14V DC, respectively. The circuits of quad op-amp U5 and Q6 and Q7 provide
steering for the oscillator in the DC-FM mode of operation. Diode CR14 provides a
stable voltage reference, which is translated to the required varactor control voltages as
required. One of the op-amps of U5 with Q6 along with the FM-STEER and
V-TC-COMP inputs and also variable resistors R35 and R39 and other resistors
provide the nominal voltage at Q7 for the correct programmed voltage V-PROG at
TP2. This is divided in the resistor string of R40, R41, R74, and R133, along with the
loop control voltage PH-DET at TP12 to provide the correct voltage VCO-CONTROL
for correct frequency of the oscillator. The control line HIDEVL is programmed by the
instrument control for either HI DEVIATION or not. The remaining sections of U5
provide the temperature compensation signal V-TCCOMP, TP9. RT1 is a temperature
sensitive resistor.
Divider Section 6E-5.
The divider section consists of two programmable divider sections: the reference
frequency divider and the variable frequency divider. The reference frequency divider
consists of U7, U8, U9, U10, and U13. The variable frequency divider consists of U12,
U14, U15, U16, U17, and U49. Each divider section respectively divides the referency
frequency and the variable frequency by the same division. The divider sections receive
20 MHz and divide to one of the following frequencies: 5 MHz, 200 kHz or 50 kHz,
which is a division by 4, 100, or 400 from the 20 MHz, or it is 16, 400, or 1600 from the
80-MHz FM oscillator. Both dividers are programmed to divide the same by the
control logic. Each divider consists of three parts: a divide-by-four section, a
divide-by-four section and a divide-by-25 section. Multiplexers U13 and U49 control
each divider section for the correct division. A division by 4 (5 MHz) uses just the first
divide-by-four. A division by 100 (200 kHz) uses the first divide-by-four and the
divide-by-25. A division by 400 (50 kHz) uses all three divider sections.
Each of the divider sections has different outputs. The reference divider section has two
outputs, a signal called "RSIG" and a signal called "Rck". The variable frequency
divider has three output signals: "VSIG", "Vckl", and "Vck2". The output signals are
used to control the phase detectors. The relationship of these signals is shown below
and is discussed in the the following paragraphs. The reference divider also has a
circuit, REF ON/OFF SWITCH, part of U6 and Q9, which controls the input 20 MHz
that comes from the output board. The circuit enables the 20 MHz from the output
board except when DCFM is active. The function of the different outputs from the
dividers is shown in Figure 6E-3, and discussed under the heading "Phase Detectors,
Loop Circuits, and Logic Section" that follows.
Within the signals of each divider the signal relationship is fixed, for example between
R & Rck, but the relationship between the RSIG signals and the VSIG signals can vary
in timing as shown by the first and second set of pulses. These signal drive the phase
detectors as will be discussed in the following paragraphs.
Phase Detectors, Loop Circuits, and Logic Section. 6E-6.
Only one of two phase detectors is active at any time. One of these, U21, is the normal,
standard dual D-flip-flop. The other, U11, is a wide range, N-PI phase detector which
uses U11, an up-down counter. The standard phase detector uses diode switched
resistor current sources; the other, the N-PI, uses a switched DAC. Also associated
with the dividers and phase detectors is an unlock detector, U20, which will respond if
an overmodulation or unlocked condition exists at the phase detector divider
combination.
6E-4
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