TROUBLESHOOTING AND REPAIR
FREQUENCY SYNTHESIS
LOOP AMPLIFIER
The loop amplifier consists of a low frequency path and a high frequency path
connected in parallel, and is driven by the phase detector voltage at the loop filter
output (L26). This configuration was chosen to minimize noise and phase shift at
frequencies around the unity loop gain frequency of 500 kHz.
The low frequency path is operative from DC to about 30 kHz, and includes OP
AMPS U104, U105, and associated components. U105 is also configured to act as a
Wien bridge type acquisition oscillator. When the sum loop is unlocked, U105
oscillates at either 800 Hz or 14 kHz, depending on switching FETs Q106-107, which
switch capacitors C127 and C131. Potentiometer R132 sets the amplitude of
oscillation. U105 stops oscillating and acts as a gain-of-3 amplifier when phase lock is
obtained, due to loop dynamics.
The high frequency path is operative for frequencies greater than about 30 kHz, and
includes Q108 and associated components. Q108 is a low noise, high f
t
transistor
configured as an emitter follower. An R-C circuit sums the outputs of the two paths,
with C137 and C138 providing high-pass and low-pass characteristics, respectively.
Loop gain adjustment is provided by R167.
The summing node, at TP4, is connected to the sum loop VCO phase lock port, J6. Six
switchable resistors, R138-143, also connect this node to ground. These switched
resistors are used to adjust loop amplifier gain to compensate for sum loop VCO Kv
variations. Note that Kv is the slope of the frequency vs. tuning voltage function. The
switched resistors are programmed by U110, a PROM that contains a look-up table.
SUMCOMP bits 0-7, a binary number proportional to 1 / Kv, is the input to U110. The
six-bit output of U110, functionally related to the SUMCOMP number, drives the
programmed resistors in a way to compensate for Kv variation with sum loop VCO RF
frequency.
ACQUISITION CIRCUITS
The acquisition circuit includes several parts, including a two frequency acquisition
oscillator, an unlock detecting comparator, a loop disabling circuit, and a dual
monostable multivibrator. These parts interact as described below.
When the loop is properly phase locked, the phase detector voltage at TP5 stays close
to 0V, because the loop forces equal frequency and nearly equal phase for the phase
detector inputs. If the loop was opened, for instance by shorting the VCO phase lock
port at TP4, the phase detector would generate a beat frequency triangle wave signal of
about 300 mV amplitude. Thus, the presence of a voltage above a threshold level
indicates loop unlock. High speed comparator U115 trips and activates a two-stage
acquisition sequence when the phase detector voltage exceeds 190 mV, indicating loop
unlock.
The output of U115 is applied to the 1A input of U114, a dual monostable
multivibrator, and trips the A one-shot upon unlock detection. One-shot A is
configured for a 10 ms output pulse, and drives comparators U102A and U102B, which
disable the low and high frequency paths of the loop amplifier, respectively, during the
10 ms pulse. U102A turns off Q109, and U102B turns off bias current to Q108,
effectively open circuiting the loop amplifier. This disabling action opens the loop and
allows time for all the frequency inputs to the Sum Loop PCA to settle to proper values
following a change in instrument RF frequency, prior to sum loop phase lock
6C-36
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