TROUBLESHOOTING AND REPAIR
FREQUENCY SYNTHESIS
acquisition. The trailing edge of the one-shot A pulse triggers one-shot B, at the 2B
input. One-shot B is configured for a 0.5 ms pulse and drives comparator U102C,
which switches acquisition oscillator U105 to the 14-kHz mode. This acquisition
frequency results in optimum lock-on behavior. During the 0.5-ms pulse, unlock
comparator U115 is disabled, to allow acquisition to occur. If Sum Loop PCA inputs
are correct, acquisition occurs during the 0.5 ms pulse, and U105 stops oscillating, due
to changes in loop dynamics. After the 0.5-ms one-shot B pulse, U105 is set to the
800-Hz mode to improve closed-loop dynamics, but doesn't oscillate if the lock was
obtained.
U102D is a zero crossing comparator that senses the polarity at TP1, the low frequency
loop amplifier output, and generates the SUMVOLH signal. The controller uses this
signal during the sum loop VCO calibration routine.
U116 is a monostable multivibrator that is triggered by the acquisition oscillation at
U105 that occurs when the sum loop is unlocked, and generates the SUMUNLKL
signal. This informs the controller that the sum loop is not locked.
SUM LOOP VCO STEERING CIRCUIT
The Sum Loop VCO has two ports for frequency tuning, the steering port at J5 and the
phase-lock-port at J6. A coarse tuning voltage, generated at the steering port, tunes the
Sum Loop VCO frequency to the desired value, within about ± 2 MHz. The phase lock
port is driven by the loop amplifier with enough voltage to compensate for the error in
the steering port and sets the Sum Loop VCO frequency to the correct phase-locked
value. The following paragraphs describe the circuit that drives the steering port.
The SUMSTEER signal at J7-14 is an RF frequency dependent DC voltage that is
proportional to the required Sum Loop VCO steering port voltage. This signal is
generated in a 12-bit DAC on the A11 Modulation Control PCA that is programmed
by data stored in the controller. Note that this data is obtained and stored during the
Sum Loop VCO compensation procedure, and is unique to a given VCO. The
SUMSTEER signal is low-pass filtered and amplified by U103 and associated
components. Gain adjustment is provided by R112. The DC voltage at the steering
port, TP3, varies from 0 to 26V, depending on RF frequency.
The source of FM in the signal generator is the 80-MHz signal from the A14 FM PCA,
an input to the sum loop. Since the Sum Loop VCO is phase locked to this signal, any
frequency modulation on the 80-MHz FM PCA signal is transferred to the Sum Loop
VCO. However, at high levels of FM deviation, the required voltage swing at the VCO
phase lock port would require a phase detector output greater than possible, and thus
the Sum Loop would lose lock. This problem is avoided by applying an AC signal at
the VCO steering port that provides nearly the correct deviation in the Sum Loop
VCO, during high deviation FM operation. Thus, the loop must only generate a small
error voltage at the VCO phase lock port to maintain lock, and the phase detector
output stays acceptably small.
The SUMAUDIO signal at J8-1 is from the A14 FM PCA and is an AC frequency
modulating signal with amplitude proportional to FM deviation. This signal is
buffered by OP AMP U106, which is configured for unity gain and can be switched via
U107 for inverting or non-inverting operation. These two modes are required to
properly phase the cancellation signal, depending on fundamental frequency band.
For f(fund) < 760 MHz, U106 inverts, while for f(fund) >= 760 MHz, U106 is
non-inverting. Gain equalization for the two modes is provided by R121. The buffered
6C-37
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