58452 VXIbus Universal Power Meter
3-10 Publication 21555, Rev. E, September 2002
3.6.1.2 Shared Memory
U29 and U30 are 32 k x 8 static RAM chips located on the Shared Bus for the development of VXI
Shared Memory Protocols.
3.6.1.3 Shared Memory Decoders
U33 generates the necessary strobes and control signals to the Shared Memory static RAMs.
3.6.1.4 Drivers & Transceivers
U36 and U37 transceivers enable the data lines from the VXI bus onto the shared bus, and vice versa.
The A1 through A15 address lines are latched by U38 and U39 latching transceivers from the VXI bus
onto the shared bus to implement address pipe-lining. The address lines are not latched going the other
way.
The U40 transceiver buffers the address modifier lines.
The VXI chip controls the direction, and enables the transceivers.
U23 and U24 latch the processor data lines D00 to D15 to drive the upper 16 address lines of the VXI
A32 space to implement A32 bus mastership.
The A24 through A31 address lines are buffered by U45 from the VXI bus P2 connector to the gate
array.
U35 is a GAL which controls the direction of the data strobes, data transfer acknowledge, and the bus
error from the VXI bus to the gate array and vice versa.
3.6.1.5 Logical Address Switch
U19 buffers the outputs of the address switch SW1 to enable the processor to read the logical address
from the switch.
3.6.1.6 TTL Triggers & Local Bus
The TTL triggers and local bus are not used by the Processor board, but are made available to be used on
the Digital board through the P7 pin connector.
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