Evaluation Board Manual
Preliminary PPC750FX Evaluation Board
750FXebm_ch1.fm
June 10, 2003
Overview
Page 15 of 115
• Decode
- Register file access.
- Forwarding control.
- Partial instruction decode.
• Load/Store unit
- One cycle load or store cache access (byte, half word, word, double word).
- Effective address generation.
- Hits under misses (one outstanding miss).
- Single-cycle misaligned access within double word boundary.
- Alignment, zero padding, sign extend for integer register file.
- Floating-point internal format conversion (alignment, normalization).
- Sequencing for load/store multiples and string operations.
- Store gathering.
- Cache and translation look-aside buffer (TLB) instructions.
- Big and little-endian byte addressing supported.
- Misaligned little-endian support in hardware.
• Fixed-point units
- FXU1: multiply, divide, shift, rotate, arithmetic, logical.
- FXU2: shift, rotate, arithmetic, logical.
- Single-cycle arithmetic, shift, rotate, logical.
- Multiply and divide support (multi-cycle).
- Early out multiply.
- Thirty-two, 32-bit general purpose registers.
• Floating-point unit
- Support for IEEE-754 standard single- and double-precision floating-point arithmetic.
- Optimized for single-precision multiply/add.
- Thirty-two, 64-bit floating point registers.
- Enhanced reciprocal estimates.
- Three-cycle latency, one-cycle throughput, single-precision multiply-add.
- Three-cycle latency, one-cycle throughput, double-precision add.
- Four-cycle latency, two-cycle throughput, double-precision multiply-add.
- Hardware support for divide.
- Hardware support for denormalized numbers.
- Time deterministic non-IEEE mode.
• System unit
- Executes CR logical instructions and miscellaneous system instructions.
- Special register transfer instructions.
• Level 1 (L1) Cache structure
- 32KB, 32-byte line, 8-way set associative instruction cache.
- 32KB, 32-byte line, 8-way set associative data cache.
- Single-cycle cache access.
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