IBM PPC750FX User Manual

Evaluation Board Manual
PPC750FX Evaluation Board Preliminary
Overview
Page 14 of 115
750FXebm_ch1.fm
June 10, 2003
The PPC750FX processor has the following features:
• Branch processing unit
- Four instructions fetched per clock.
- One branch processed per cycle (plus resolving two speculations).
- Up to one speculative stream in execution, one additional speculative stream in fetch.
- 512-entry branch history table (BHT) for dynamic prediction.
- 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay
slots.
• Dispatch unit
- Full hardware detection of dependencies (resolved in the execution units).
- Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1
(FXU1), fixed-point unit 2 (FXU2), or floating-point).
- Four-stage pipeline: fetch, dispatch, execute, and complete.
- Serialization control (predispatch, postdispatch, execution, serialization).
Figure 1-1. PPC750FX Block Diagram
FXU2
GPRs
LSU FPU
Instruction Fetch
System
Completion
Rename
Buffers
Unit
32KB I-Cache
32KB D-Cache
BHT/BTIC
BIU
Enhanced
512KB
FXU1
L2 Tags
Dispatch
Branch Unit
Control Unit
FPRs
Rename
Buffers
with ECC
60X
with parity
with parity
L2 Cache

IBM PPC750FX Specifications

General

Brand	IBM
Model	PPC750FX
Category	Motherboard
Language	English