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Evaluation Board Manual

PPC750FX Evaluation Board Preliminary

Reset and Interrupts

Page 38 of 115

750FXebm_ch5.fm

June 10, 2003

Table 5-1. External Interrupts

MPP Controller Pin +/- Active Sensitivity Description

25 + level UART Channel A

26 + level UART Channel B

27 – level Ethernet PHY

28 – level PCI Intr A

29 – level PCI Intr B

30 – level PCI Intr C

31 – level PCI Intr D

Note: The PCI interrupts are inputs when the board is operating as a PCI host. If operating as a PCI adapter, these pins should be

configured as outputs.

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IBM PPC750FX Specifications

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