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PPC750FX
IBM PPC750FX User Manual
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Eval
uati
on B
oard
Manu
al
Preliminary
PPC750
FX Evalua
tion Board
750FXebm_ch11.fm
June 10, 2003
CPLD Program
ming
Page 89 o
f 115
1
1.1.2.6
reset_block Program
The foll
owing co
de listing d
efines the fun
ction of t
he logic in
the
reset_block
part of the
CPLD:
INCLUDE "lpm_ff.inc";
SUBDESIGN reset_bloc
k
(
25Mclk
: INPUT
;
rw_hreset
:
INPUT
;
rw_sreset
:
INPUT
;
rw_trst
: INPUT
;
mpp_reset_
2ms_n: INPUT
;
mpp0_hreset_n
:
INPUT
;
mpp0_sreset_n
: INPUT
;
mpp1_hreset_n
:
INPUT
;
mpp1_sreset_n
: INPUT
;
mpp_reset_
out_n
: INPUT
;
initact
:
INPUT
;
pgd
: INPUT
;
target/ho
st_n
: INPUT
;
serial_
eeprom
: INPU
T
;
pci_reset_
n
:
BIDIR;
sysre
set_n
: OUT
PUT
;
cpu0_h
reset_n
: OUTPUT
;
cpu0_s
reset_n
: OUTPUT
;
cpu1_h
reset_n
: OUTPUT
;
cpu1_s
reset_n
: OUTPUT
;
cpu_trs
t_n
: OUTPUT
;
cpufan_
ok_n
: INPUT
;
ignore_f
ans_n
: INPUT
;
mpp_bl
ock_n
: INPUT
;
nofa
n_n
: OUTP
UT
;
sloclk
: OUT
PUT
;
A
TX_OK_N
: INPUT
;
led_red_
n
: OUTPUT
;
sysrese
t
:
OUTPUT
;
)
V
ARIABLE
del_rw_hre
s
et[1.
.0]: df
f;
del_rw_s
reset[1
..0]: df
f;
del_rw_trs
t[1..0]
: dff;
88
90
Table of Contents
Default Chapter
1
Evaluation Board
1
Table of Contents
3
Tables
7
Figures
9
About this Book
11
1 Overview
13
Powerpc 750FX RISC Microprocessor Features
13
Figure 1-1. PPC750FX Block Diagram
14
Board Features
17
2 Board Design
19
Processor
19
Figure 2-1. PPC750FX Board Architecture
19
Board Clocking
20
Figure 2-2. Clock Distribution on the PPC750FX Board
20
Internal Processor Clocking
21
System Controller
21
SDRAM Interface
21
PCI Bus
21
Ethernet
21
Table 2-1. Ethernet Ports
21
Flash Memory
22
Figure 2-3. Board Ethernet Architecture
22
Table 2-2. Switch Settings
23
Table 2-3. Flash Configurations
23
Nvram
24
Sram
24
Serial Ports
24
Figure 2-4. Board Serial Port Architecture
24
Logic Analyzer Connections
25
Power Supply
25
PCI Voltages
25
System Controller Voltages
25
PPC750FX Voltages
25
SDRAM Voltages
26
Form Factor
26
3 Memory Map
27
CPLD Register Definitions
27
Table 3-1. Board Address Space Usage
27
Table 3-2. Register0
27
Table 3-3. Register1
28
Table 3-4. Register2
28
Table 3-5. Register3
29
Table 3-6. Register4
29
4 Programming the System Controller
31
Ddr Sdram
31
SDRAM Controller Initialization
31
Device Controller Bank Register Settings
31
Table 4-1. DDR SDRAM Characteristics
31
Device Bank 0 Parameters (32-Bit Flash)
32
Table 4-2. Device Bank 0 Parameters = 0X85A492Bf
32
Device Bank 1 Parameters (CPLD Registers)
33
Table 4-3. Device Bank 1 Parameters = 0X8004921A
33
Device Bank 2 Parameters (Uarts)
34
Table 4-4. Device Bank 2 Parameters = 0X8C002Bd6
34
Device Bank 3 Parameters (FRAM)
35
Table 4-5. Device Bank 3 Parameters = 0X8D891445
35
Boot Device Parameters (8 Bit Flash and SRAM)
36
Table 4-6. Boot Device Bank Parameters = 0X8185D09E
36
5 Reset and Interrupts
37
Resets
37
Interrupts
37
Figure 5-1. Interrupt Architecture
37
Table 5-1. External Interrupts
38
6 Switches
39
Reset Pushbutton
39
Table 6-1. Switches
39
Table 6-2. Reset Pushbutton-U5
39
Figure 6-1. Switch Location Diagram
39
ATX Power-On Pushbutton
40
CPU 0 PLL Configuration
40
Table 6-3. Reset Pushbutton-U53
40
Table 6-4. CPU 0 PLL Configuration-U30
40
CPU 1 PLL Configuration
41
Table 6-5. CPU 1 PLL Configuration Switches-U35
41
System Controller Initialization
42
Table 6-6. System Controller Initilization-U17
42
Table 6-7. System Controller Initilization-U24
43
7 Fuses, Batteries, Regulators, and Fans
45
On-Board Current Monitoring and Variable Voltage Testing
45
Supplies
45
Table 7-1. Current Measurement of The1.4V Supplies
45
Figure 7-1. Resistor Location Diagram
45
Supply
46
Fan
46
Table 7-2. Current Measurement of the 2.5V Supply
46
Figure 7-2. Fan and Heatsink Location Diagram
46
8 Displays
47
Table 8-1. Displays
47
Figure 8-1. Display Location Diagram
47
9 Jumpers
49
Figure 9-1. Jumper Location Diagram
49
Table 9-1. Jumpers
49
Figure 9-2. Write-Protect 32-Bit Flash Memory Jumper-J8
50
Figure 9-3. Ignore Fan Jumper-J16
50
Ignore Fan
50
Table 9-2. Write-Protect 32-Bit Flash Memory-J8
50
Table 9-3. Ignore Fans-J16
50
Write-Protect 32-Bit Flash
50
Figure 9-4. PCI Interrupt Selection Jumper-J22
51
PCI Interrupt Selection
51
Table 9-4. PCI Interrupt Selection-J22
51
10 Connectors
53
Table 10-1. Connectors
53
Figure 10-1. Connector Location Diagram, Top Side
54
Auxiliary Power
55
Figure 10-2. ATX Power Supply Connector-J34
55
Table 10-2. ATX Power Signals-J34
55
Fan Power
56
Figure 10-3. Ground Connectors-J1, J2, J7, J9, J10, J12, J17, J18, J23, J24
56
Figure 10-4. Fan Power Connector-J4
56
Ground
56
Table 10-3. Ground Connectors -J1, J2, J7, J9, J10, J12, J17, J18, J23, J24
56
Table 10-4. Fan Power Signals-J4
56
Figure 10-5. Riscwatch JTAG Connector-J11
57
Riscwatch JTAG Debugger
57
Table 10-5. Riscwatch Signals-J11
57
Ethernet
58
Figure 10-6. Ethernet Connector-One of Two RJ45 Sockets in J20
58
Table 10-6. Ethernet UTP Signals-J20, both Sockets
58
Figure 10-7. PCI Connector-J25
59
PCI Connector
59
Table 10-7. PCI Connector Signals-J25
59
CPLD JTAG Connector
62
Figure 10-8. CPLD JTAG Connector-J26
62
Table 10-8. CPLD JTAG Connector-J26
62
Figure 10-9. Serial Port Connector-J13, One of Two RJ11/12 Sockets
63
Serial Ports
63
Table 10-9. Serial Port Connector Signals-J13, both Ports
63
Figure 10-10. System Controller Device Address Connector-J14
64
System Controller Device Address Bus
64
Table 10-10. System Controller Device Address Signals-J14
64
Figure 10-11. Memory Control Connector-J15
66
Memory Control
66
Table 10-11. Memory Control Signals-J15
66
External Clock Input
68
Figure 10-12. External Clock Input Connector-U39
68
Table 10-12. External Clock Input Signal-U39
68
Table 10-13. Test Connections
69
Test Connections
69
Figure 10-13. Test Connection Locations
71
11 CPLD Programming
73
Programming-Registers and Control Functions
73
I/O Pin List
73
Table 11-1. Section Contents
73
Table 11-2. CPLD I/O Pin List
73
CPLD Logic
76
Table 11-3. CPLD Logic Descriptions
76
Top Level Block Diagram 1
77
Top Level Block Diagram 2
78
Framcs Logic
79
Decode_Block Program
80
Registers2 Program
84
Reset_Block Program
89
Misc Logic
93
Timing-Registers and Control Functions
94
Maximum Clock Frequency
94
Clock-To-Output Time
94
Table 11-4. Maximum Clock Frequency
94
Table 11-5. Clock-To-Output Time
94
Pin-To-Pin Signal Delay
96
Table 11-6. Pin-To-Pin Signal Delay
96
Setup and Hold Time
100
Table 11-7. Setup and Hold Time
100
12 Bills of Materials
101
Component Location
101
Table 12-1. Section Contents
101
Table 12-2. Component Placement Data Description
102
Figure 12-1. Example of a Component Placement List in the Schematics
102
Figure 12-2. Board Location Grid-Top View
103
Figure 12-3. Board Location Grid-Bottom View
103
Debugging Tools
104
Auxiliary Materials
104
Table 12-3. Debugging Tools
104
Table 12-4. Auxiliary Materials in Kit
104
Board Bill of Materials
105
Table 12-5. Evaluation Board Bill of Materials
106
Index
113
Revision Log
115
4
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IBM PPC750FX Specifications
General
Brand
IBM
Model
PPC750FX
Category
Motherboard
Language
English
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