Evaluation Board Manual
Preliminary PPC750FX Evaluation Board
750FXebmLOF.fm
June 10, 2003
Figures
Page 9 of 115
Figures
Figure 1-1. PPC750FX Block Diagram ..................................................................................................... 14
Figure 2-1. PPC750FX Board Architecture .............................................................................................. 19
Figure 2-2. Clock Distribution on the PPC750FX Board ........................................................................... 20
Figure 2-3. Board Ethernet Architecture ................................................................................................... 22
Figure 2-4. Board Serial Port Architecture ................................................................................................ 24
Figure 5-1. Interrupt Architecture .............................................................................................................. 37
Figure 6-1. Switch Location Diagram ....................................................................................................... 39
Figure 7-1. Resistor Location Diagram ..................................................................................................... 45
Figure 7-2. Fan and Heatsink Location Diagram ...................................................................................... 46
Figure 8-1. Display Location Diagram ...................................................................................................... 47
Figure 9-1. Jumper Location Diagram ...................................................................................................... 49
Figure 9-2. Write-Protect 32-bit Flash Memory Jumper—J8 .................................................................... 50
Figure 9-3. Ignore Fan Jumper—J16 ....................................................................................................... 50
Figure 9-4. PCI Interrupt Selection Jumper—J22 ..................................................................................... 51
Figure 10-1. Connector Location Diagram, Top Side ................................................................................. 54
Figure 10-2. ATX Power Supply Connector—J34 ......................................................................................55
Figure 10-3. Ground Connectors—J1, J2, J7, J9, J10, J12, J17, J18, J23, J24 ........................................ 56
Figure 10-4. Fan Power Connector—J4 ..................................................................................................... 56
Figure 10-5. RISCWatch JTAG Connector—J11 ....................................................................................... 57
Figure 10-6. Ethernet Connector—One of two RJ45 Sockets in J20 ......................................................... 58
Figure 10-7. PCI Connector—J25 ............................................................................................................. 59
Figure 10-8. CPLD JTAG Connector—J26 ................................................................................................ 62
Figure 10-9. Serial Port Connector—J13, one of two RJ11/12 sockets ..................................................... 63
Figure 10-10. System Controller Device Address Connector—J14 ............................................................. 64
Figure 10-11. Memory Control Connector—J15 ........................................................................................... 66
Figure 10-12. External Clock Input Connector—U39 ................................................................................... 68
Figure 10-13. Test Connection Locations ..................................................................................................... 71
Figure 12-1. Example of a Component Placement List in the Schematics ............................................... 102
Figure 12-2. Board Location Grid—Top View ........................................................................................... 103
Figure 12-3. Board Location Grid—Bottom View .....................................................................................103