Evaluation Board Manual
Preliminary PPC750FX Evaluation Board
750FXebm_ch3.fm
June 10, 2003
Memory Map
Page 29 of 115
Table 3-5. Register3
Bit Name R/W Description
0 (msb) Block MPP resets R/W
Five MPP/GPP pins on the system controller can be used to control
the SRESET and HRESET of pins of the processors, and an entire
board reset. To give software a chance to configure the MPP/GPP
pins 7, 8, 11, 12, and 24 properly, the signals are blocked by the
CPLD until this bit is set to 1.
0 = MPP resets are blocked
1 = MPP resets are not blocked
1:7 unused
Table 3-6. Register4
Bit Name R/W Description
0:7 Board Revision R
Board revision level in binary (for example, 0x00000010 = Revision
level 2).
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