IBM PPC750FX - Page 75

Evaluation Board Manual
Preliminary PPC750FX Evaluation Board
750FXebm_ch11.fm
June 10, 2003
CPLD Programming
Page 75 of 115
cpu0_hreset_n 52 Output
cpu_trst_n 53 Output
cpu1_sreset_n 54 Output
cpu1_hreset_n 55 Output
cpu0_sreset_n 56 Output
lcs_n[1] 57 Input
mpp_reset_out_n 58 Input
GND 59 Gnd
~VREFB~ 60 Input
atx_ok_n 61 Input
~TCK~ 62 Input
dev_we_n[0] 63 Input
lcs_n[0] 64 Input
bootsmall_n 65 Input
VCCIO2 66 Power
badr[2] 67 Input
rw_sreset 68 Input
jtag_chkstop_n 69 Output
cpu_tben 70 Output
cpu1_smi_n 71 Output
cpu0_smi_n 72 Output
~TDO~ 73 Output
GND 74 Gnd
lcs_n[3] 75 Input
mpp0_hreset_n 76 Input
ldev_addr[21] 77 Input
cstiming_n 78 Input
unused_pin 79 Output
cpu_mcp1 80 Output
cpu_mcp0 81 Output
VCCIO2 82 Power
mpp1_sreset_n 83 Input
rw_hreset 84 Input
switch_b 85 Input
GND 86 Gnd
pld_sysclk 87 Input
target/host_n 88 Input
Table 11-2. CPLD I/O Pin List (Continued)
Name Pin Function