IBM PPC750FX - Page 91

Evaluation Board Manual
Preliminary PPC750FX Evaluation Board
750FXebm_ch11.fm
June 10, 2003
CPLD Programming
Page 91 of 115
-- Cascade tff’s - create a 2 bit counter
-- that runs at the full rate. AND the output bits together
-- and whenever count = "11" a pulse is generated.
-- Use that 1/4 rate pulse as an enable for the dff’s.
sloclk3[].clk = 25Mclk;
sloclk3[].d = sloclk3[].q + 1;
sloclk3_ = sloclk3[1] & sloclk3[0];
-- delay pgd using 25Mhz clock
del_pgd_.clock = 25Mclk;
del_pgd_.enable = sloclk3_;
del_pgd_.data[0] = pgd;
del_pgd_.data[1] = del_pgd_.q[0];
del_pgd_.data[2] = del_pgd_.q[1];
del_pgd_.data[3] = del_pgd_.q[2];
del_pgd_.data[4] = del_pgd_.q[3];
del_pgd_.data[5] = del_pgd_.q[4];
del_pgd_.data[6] = del_pgd_.q[5];
del_pgd_.data[7] = del_pgd_.q[6];
del_pgd = del_pgd_.q[0] & del_pgd_.q[1] & del_pgd_.q[2] & del_pgd_.q[3]
& del_pgd_.q[4] & del_pgd_.q[5] & del_pgd_.q[6] & del_pgd_.q[7];
-- this circuitry below is a filter and designed to provide cleaner signals to CPU
-- *** hreset logicstart
del_rw_hreset[1..0].clk = 25Mclk;
del_rw_hreset[0].d = rw_hreset;
del_rw_hreset[1].d = del_rw_hreset[0].q;
cpu0_hreset_n_ = !(initact & serial_eeprom)
& (del_rw_hreset[0].q & del_rw_hreset[1].q)
& sysreset_n & del_sysreset_n
& (mpp0_hreset_n # !mpp_block_n);
cpu0_hreset_n = cpu0_hreset_n_;
cpu1_hreset_n_ = !(initact & serial_eeprom)
& (del_rw_hreset[0].q & del_rw_hreset[1].q)
& sysreset_n & del_sysreset_n
& (mpp1_hreset_n # !mpp_block_n); -- Ver 10 test
cpu1_hreset_n = cpu1_hreset_n_;
-- *** hreset logicend
-- *** sreset logicstart
del_rw_sreset[0].d = rw_sreset;
del_rw_sreset[1..0].clk = 25Mclk;