Evaluation Board Manual
Preliminary PPC750FX Evaluation Board
750FXebm_ch11.fm
June 10, 2003
CPLD Programming
Page 95 of 115
dev_adr[2] dev_we_n[0] 9.400 9.400
dev_adr[3] ale 12.500 12.500
dev_adr[3] dev_we_n[0] 9.400 9.400
dev_adr[4] ale 12.500 12.500
dev_adr[4] dev_we_n[0] 9.400 9.400
dev_adr[5] ale 12.500 12.500
dev_adr[5] dev_we_n[0] 9.400 9.400
dev_adr[6] ale 12.500 12.500
dev_adr[6] dev_we_n[0] 9.400 9.400
dev_adr[7] ale 12.500 12.500
dev_adr[7] dev_we_n[0] 9.400 9.400
led_red_n pld25mhz 9.500 9.400
led0 dev_we_n[0] 5.700 5.700
led1 dev_we_n[0] 5.700 5.700
led2 dev_we_n[0] 5.700 5.700
nvram_cs_n ale 18.500 18.500
nvram_cs_n pld_sysclk 23.100 17.700
pci_reset_n pld25mhz 9.500 9.500
read_n ale 9.400 9.400
small_flash_cs_n ale 9.100 9.100
small_flash_hi_cs_n ale 9.100 9.100
sram_cs_n ale 9.100 9.100
sram_hi_cs_n ale 9.100 9.100
sysreset pld25mhz 14.500 14.400
sysreset_n pld25mhz 14.500 14.400
textpin_d ale 9.300 9.300
uart_cs_n pld_sysclk 10.500 9.000
write_n ale 9.800 9.800
write_n pld_sysclk 11.300 9.800
Table 11-5. Clock-to-Output Time (Continued)
Output Signal Clock Longest Delay (ns) Shortest Delay (ns)
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