Intel
®
EP80579 Integrated Processor with Intel
®
QuickAssist Technology—System Overview
Development Kit User’s Guide October 2008
24 Order Number: 320067-002US
3.4 SMBus
The Intel
®
EP80579 Development Board provides system management communication
through SMBus connectivity. The SMBus is implemented as a single bus with three
repeaters used for voltage translation, fan out and isolation on the Intel
®
EP80579
Development Board. Figure 7 shows the block diagram of the SMBus system on the
Intel
®
EP80579 Development Board.
§ §
Figure 7. SMBus System Block Diagram
EP80579
IICH
VSBY3_3
PCA9515
SMBus A Repeater
PCA9515
SMBus B Repeater
PCA9515
SMBus C Repeater
EP80579
IMCH
Addr 0x60
CK410
Addr 0XD2
DB800
Addr 0xDC
JTAG Debug Port
Master
DIMM_0
Addr 0xA4
DIMM_1
Addr 0xA6
Mezzaine 0
Addr Determined by Card
Mezzaine 1
Addr Determined by Card
Mezzaine 2
Addr Determined by Card
LEB Connector
Addr Determined by Card
MEZZ_SMB*
DIMM_SMB*
MCH_SMB*
VSBY_SMB*
VCC3VCC3 VCC3
SMBus header*
Note:
SMBus header is a 1x3 for header 1:DATA 2:GND 3:CLK
* in Netnames represents CLK and DAT
SMLink[0] = CLK and SMLink[1] = DAT
SMBSCL and SMBSDA from IMCH
SMBus header C*SMBus header B*
SMBus header A*
EP80579
SM Link
Addr 0x44
SMBus header
1 Data
2 Ground
3 Clock
0-ohm
VSBY_SMB*
LAN controller
SMLink*
EN EN EN
GPO23 GPO21
GPO20
Default Disable
Default Enable
Default Disable
SIO Addr 0x5C
SDA
SCLK
SDA1
SCLK1
SDA2
SCLK2
Board ID
TPM is not connected
to SMBus
SMBus header SIO1*
VSBY3_3
PCI Exp x8 Conn
(Slot #1)
PCI Exp x4 Conn
(Slot #2)
PCI Exp x4 Conn
(Slot #3)
PCI Exp x4 Conn
(Slot #4)
PCI Exp x4 Conn
(Slot #5)
VSBY3_3
SMBus header SIO2*
0-ohm
SIO2_SMB*
P
C
I
E
_
S
M
B
*
0-ohm empty0-ohm empty
0-ohm
SIO1_SMB*
S
I
O
1
_
I
D
_
S
M
B
*
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